We acknowledge the following financial support; Grant-in-Aid for Specially Promoted Research (No. 25000003) from JSPS, Grant-in-Aid for Research Activity Start-up (No.15H06133) and Challenging Research (Exploratory) (No. JP17K18748) from MEXT of Japan.

1. Dispersion of WS 2 Nanotubes (NTs) on substrate
<ol>
	<li>Disperse WS2 NT powders into isopropyl alcohol (IPA, concentration more than 99.8%) with proper diluted ratio (about 0.1 mg/mL) by sonication for 20 min. 
	NOTE: The long-time sonication helps to make WS2 NTs uniformly suspended in IPA liquid and to separate well-formed individual WS2 NTs from amorphous WS2 or other junks, as well as to remove the garbage accumulating on WS2 NTs surface. Figure 2b shows the final suspension of WS2 NTs. Since the suspension might be heated up during the sonication process, it is better to stop sonication at every 5 min and continue sonication after 1 min.</li>
	<li>Spin-coating procedure to disperse WS2 NTs on substrate.
	<ol>
		<li>Start the spin-coater machine and vacuum pump. Put a Si/SiO2 (3000 &#197;) substrate (1 cm x 1 cm) on the center of the chuck and fix it by vacuum with pumping speed of 80 L/min and ultimate pressure of 20 kPa. 
		NOTE: There is a hole located at the center of the chuck connecting to the vacuum pump, thus the substrate is fixed by vacuum pressure (pumping speed is 80 L/min and ultimate pressure is 20 kPa). The vacuum pressure can be different depending on the pump.</li>
		<li>Set relevant parameters of the procedure by control panel of the spin-coater machine. 
		NOTE: There are three steps during the spin-coating procedure: (1) slowly speed up to 500 rpm within the first 3 s, (2) rapidly speed up to 4000 rpm and continue for 50 s, (3) slow down and stop spinning for the last 3 s. Those parameters can be different depending on the use of spin-coater.</li>
		<li>Put one droplet (about 0.01 mL) of the suspension of WS2 NT made in (1.1) by a pipette onto the substrate until the substrate is fully covered by the suspension (if not, put more droplets). Then start spin-coating with relevant parameters in (1.2.2).</li>
	</ol>
	</li>
</ol>
2. Preparation of thin flake on substrate via scotch tape method
<ol>
	<li>Put a small bulk sample of WS2 (grown via chemical vapor transport method) on scotch tape. Fold the scotch tape and unfold it slowly to mechanically exfoliate the thin layer from the bulk. Repeat this procedure for several times, until the exfoliated samples are thin enough. 
	NOTE: Figure 2g and 2h show the initial tape with little bulk sample of WS2 and the final tape after multiple folding procedures, respectively.</li>
	<li>Paste the scotch tape on the top of substrate upside down, slightly press the tape, and carefully remove the tape from the top of substrate. 
	NOTE: After removing the tape, there are many thin flakes left on the substrate.</li>
</ol>
3. Device fabrication by electron beam lithography.
<ol>
	<li>Spin-coating process to cover the resist for electron beam lithography.
	<ol>
		<li>Follow the same spin-coating procedure described in (1.2.1) and (1.2.2).</li>
		<li>Put one droplet (about 0.04 mL) of polymethyl methacrylate (PMMA) by a pipette onto the substrate until the substrate is fully covered by PMMA. Then start spin-coating procedure to uniformly cover PMMA on WS2 sample to prevent it from being exposed in air. 
		Note: PMMA is one of the resists for electron beam lithography.</li>
		<li>After spin-coating, put the substrate on hot-plate at 180 &#176;C and heat it for 1 min. 
		NOTE: Those parameters can be different depending on resist types.</li>
	</ol>
	</li>
	<li>Sample selection by optical microscopy.
	<ol>
		<li>Start the optical microscopy and camera. Put the substrate on the stage.</li>
		<li>Move stage and scan the whole region of the substrate with proper magnification (20X) and in the meantime, select isolated samples with suitable size. 
		Note: In total, 6 to 10 isolated samples can be usually selected for each substrate of 1 cm x 1 cm.</li>
		<li>Take photos of each selected sample with different magnification of 5X, 20X, and 100X. Those photos are used to identify the location of each sample.</li>
	</ol>
	</li>
	<li>Design of the large-scale device pattern.
	<ol>
		<li>Activate the AutoCAD software, and load the format of substrate lattice. Insert photos taken in (3.2) and identify the size and location of each photo depending on the marks on the substrate.</li>
		<li>Insert a large square with length of 1200 &#181;m and a small square with length of 300 &#181;m which should surround each sample.</li>
		<li>Design large-scale patterns including gate, source, drain, and other pads in the large square except for fine structures near the sample. Design small marks close to the sample to precisely identify the location of the samples in the later process of design for the small-scale device pattern.</li>
		<li>Repeat (3.3.2) to (3.3.3) for every sample.</li>
		<li>Record the coordinates of the center of each large and small square, respectively.</li>
		<li>Delete inserted photos, large and small squares, and substrate lattice format, leaving only the designed large patterns and small marks. Export large patterns and small marks as dxf files, respectively.</li>
	</ol>
	</li>
	<li>First electron beam lithography.
	<ol>
		<li>Put the substrate on the stage and fix it, and insert the stage into the main chamber of electron beam lithography machine.</li>
		<li>Activate ECA program (a program for generating a file used in electron beam process). Set field size as 300 for the lithography of small marks. Use tool of dxf converter to transfer dxf file to cell file.</li>
		<li>Load the cell file generated in (3.4.2), enter the file name, identify origin and identify points with coordinates of small squares noted in (3.3.5). Finally, identify the coordinates of large A and B marks and small A and B marks for each point. 
		Note: The large A and B marks are used to correct the direction of stage, while small A and B marks are used to identify the mismatch between designed pattern and printed pattern, during the process of small-scale pattern design.</li>
		<li>Save the file as con file and wait until the pressure inside the main chamber is lower than 5x10-5 Pa. 
		NOTE: Because the electron beam is high energy (50 kV of accelerating voltage), the high quality of vacuum is needed.</li>
		<li>When the pressure of the main chamber becomes low enough for the electron beam lithography process, activate electron beam control program ESL-7500 and subsequently turn on the electron gun.</li>
		<li>Turn on the scanning electron microscope (SEM) and move the stage to the position where the substrate is in the screen. Tune the brightness, contrast, and focus.</li>
		<li>Adjust the angle of the stage by judging from the relative position of large A and B marks originally designed on the substrate until the error of direction is negligible at magnification of 5000X. After correcting the direction of the stage, register the position of the large A mark.</li>
		<li>Set the amplitude of electron beam for lithography; 100 pA is for small marks lithography. Move the stage to the position for amplitude tuning and select the spot mode for the camera, change the amplitude of electron beam until it reaches 100 pA by ampere meter. After setting the amplitude of electron beam, tune the brightness, contrast, and focus.</li>
		<li>Load saved con file in (3.4.4) in the ECA program. Set relevant parameters: 2 s for dose time and 300 for field size. Finally start the exposure process. 
		Note: Dose time can be different depending on the resist.</li>
		<li>Back to electron beam control program ESL-7500, set 5000X of magnification and move the stage to the registered position of the large A mark. Confirm the position of the large A and B marks.</li>
		<li>Set 30000X of magnification and confirm the position of small A and B marks for the lithography of the first small marks designed in (3.3.3). 
		Note: The lithography starts after conforming small marks and takes several second.</li>
		<li>After finishing the lithography, repeat this procedure for all samples. At the last, quit the exposure process and close the ECA program.</li>
		<li>Follow the same process from (3.4.2) to (3.4.10) with different parameters for the lithography of the large pattern designed in (3.3.3). In (3.4.2), set field size as 1200. In (3.4.3), only identify coordinates of large A and B marks except for small A and B marks. In (3.4.8), set the amplitude of electron beam as 1000 pA for the lithography of the large pattern. In (3.4.9), select 1200 of field size. 
		Note: After the process of (3.4.10), the lithography of the large pattern starts and takes several hours.</li>
		<li>After finishing the lithography of the large pattern, move the stage to the original position, turn off the electron beam, and quit the exposure process and the ECA program. Open the main chamber and take out the substrate.</li>
	</ol>
	</li>
	<li>First developing.
	<ol>
		<li>Make a solution of methyl isobutyl ketone (MIBK) and IPA with the ratio of MIBK: IPA = 1: 3. Dip the substrate in the solution for 30 s, and wash it by IPA liquid and dry it by nitrogen gun. 
		NOTE: Developing time may change depending on the environmental conditions such as temperature and humidity.</li>
		<li>Take photos by optical microscopy for each printed pattern with different magnification of 5X, 20X, and 100X.</li>
	</ol>
	</li>
	<li>Design of small-scale device pattern.
	<ol>
		<li>Follow the same process in (3.3). In (3.3.1), load the pattern of substrate lattice including the designed small marks in (3.3.3), and insert photos taken after first developing. 
		NOTE: The size and location of each photo depends on the small marks designed in (3.3.3), instead of marks on the substrate.</li>
		<li>Design the fine structure of device pattern with source, drain and other electrodes in small squares in a Hall bar configuration, which is connected to the printed large pattern. After designing small patterns for all the devices, record the coordinates of small squares.</li>
		<li>Delete inserted photos, small squares, and substrate pattern, leaving only the designed small patterns. Export the small pattern as dxf file.</li>
	</ol>
	</li>
	<li>Second electron beam lithography.
	<ol>
		<li>Follow the same process from (3.4.1) to (3.4.11) with the same parameters for the lithography of the small pattern designed in (3.6); set 300 for field size and select 100 pA for the amplitude of electron beam. 
		NOTE: The lithography process takes several minutes for each small pattern.</li>
		<li>After the lithography of small pattern, move the stage to the original position, turn off the electron beam, quit the exposure process and close the ECA program. Open the main chamber and take out the substrate.</li>
	</ol>
	</li>
	<li>Second developing.
	<ol>
		<li>Follow the same process in (3.5) with the same developing time as 30 s.</li>
		<li>Take photos by optical microscopy for each pattern with different magnification of 5X, 20X, and 100X.</li>
	</ol>
	</li>
</ol>
4. Deposition of electrodes
<ol>
	<li>Deposition of gold electrodes.
	<ol>
		<li>Fix the substrate on substrate holder, put the substrate holder on transfer rod, and insert it into the main chamber of the evaporator. Start rotating the substrate holder.</li>
		<li>First deposit Cr of 5 nm in thickness as the adhesion layer. When the pressure inside the main chamber becomes less than 10-4 Pa, turn on the high voltage source.</li>
		<li>Increase the current of electron gun carefully with the fixed accelerating voltage of 4 kV, until the depositing rate measured by thickness monitor becomes stable about 0.5 &#197;/s (usually pre-evaporate Cr of about 5 nm).</li>
		<li>Open the shutter and deposit Cr until it reaches 5 nm in thickness. Close the shutter, slowly decrease the current of electron gun to zero, and turn off the high voltage source.</li>
		<li>Subsequently deposit Au of appropriate thickness. Turn on the current source and slowly increase the current up to 30 A. Evaporate Au by keeping the current of 30 A, until the depositing rate measured by thickness monitor becomes stable about 1 &#197;/s (usually pre-evaporate Au of about 10 nm ).</li>
		<li>Open the shutter and start depositing Au. After reaching the intended thickness, close the shutter, slowly decrease the current to zero, and turn off the current source. 
		Note: We use 60 nm for thin flake and 90 nm for NT. The appropriate thickness is depending on the sample.</li>
		<li>Since the substrate is heated up during deposition process, remain the substrate inside the chamber for 1 h in order to cool down its temperature to near room temperature. Stop rotating the substrate holder and take it out by transfer rod.</li>
	</ol>
	</li>
	<li>Deposition of SiO2 protection layer.
	<ol>
		<li>With the help of optical microscopy, cover the pads and the gate electrodes by tape. 
		NOTE: In principle, only the fine structures of electrodes are exposed to deposit SiO2 layer for the protection of electrodes against the chemical reaction during the electrolyte gating.</li>
		<li>Follow the same process from (4.1.1) to (4.1.4) to deposit Cr of 5 nm in thickness as adhesion layer.</li>
		<li>Subsequently follow the same process from (4.1.1) to (4.1.4) to deposit SiO2 of 20 nm in thickness. 
		Note: The depositing rate of SiO2 is about 1 &#197;/s, while pre-evaporating SiO2 of about 10 nm.</li>
		<li>Cool down the substrate inside the chamber for 1 h. Stop rotating the substrate holder and take it out by the transfer rod. Remove the tape under microscopy.</li>
	</ol>
	</li>
</ol>
5. Completion of the device
<ol>
	<li>Substrate scribing.
	<ol>
		<li>Turn on the scribing machine and vacuum pump with pumping speed of 50 L/min and ultimate pressure of 30 kPa. Fix the substrate on the stage by vacuum chuck and adjust the angle and position of the substrate.</li>
		<li>Scribe the substrate into small pieces (usually about 3 mm x 3 mm). 
		Note: The size of each piece is depending on the location of each selected sample and the designed pattern.</li>
	</ol>
	</li>
	<li>Device lift-off.
	<ol>
		<li>Select one device and immerse it into acetone (concentration more than 99.5%) for 1 h at room temperature to remove the redundant PMMA and gold. Only the fabricated electrodes are left on substrate.</li>
		<li>After the lift-off process, wash the substrate by IPA and dry it by nitrogen gun.</li>
	</ol>
	</li>
	<li>Wire-bonding.
	<ol>
		<li>Turn on the wire-bonding machine. Fix the substrate on the chip-carrier via sliver paste. 
		NOTE: For WS2 NT case, we use horizontal rotator shown in Figure 2n.</li>
		<li>With the help of wire-bonding machine, connect each electrode pad and electrode of chip carrier one by one with a gold wire.</li>
	</ol>
	</li>
	<li>Electrolyte droplet putting.
	<ol>
		<li>Put a droplet of electrolyte (less than 0.5 &#181;L) on the top of device by a tweezer after dipping in the electrolyte liquid. 
		NOTE: The amount of electrolyte is very little; it covers the fine structure of device and gate pad but avoids covering the electrode pads. We use the electrolyte of KClO4 (concentration more than 99%) dissolved in polyethylene glycol (PEG; Mw = 600) with a [K]:[O] ratio of 1:20 according to the previous publication38.</li>
	</ol>
	</li>
</ol>
6. Transport measurements
<ol>
	<li>Fix the chip-carrier on the sample holder, and put it inside the chamber of physical properties measurement system by the transfer rod. Pump the chamber by the high vacuum mode.</li>
	<li>Connect measurement system including lock-in amplifiers, nano-voltmeter, source meter, and amplifier. Apply a constant alternating current (AC) with the frequency of 13 Hz to perform the AC-lock-in measurements.</li>
	<li>Run the Keysight VEE program (measurement programs).</li>
	<li>In the measurement of gate response, when the gate voltage is applied to the electrolyte (i.e., between source and gate electrodes), sweep the gate voltage with speed of 50 mV/s at 300 K, under high-vacuum condition to reduce the influence of the air on the gating performance.</li>
	<li>In the measurement of temperature dependence of resistance, first cool down to 200 K with the cooling rate of 1 K/min in high-vacuum condition, and then change to the He-purged condition and keep cooling down to 10 K with the cooling rate of 1 K/min. When the temperature is lower than 10 K, cool down and warm up with the rate of 0.2 K/min. 
	Note: In the He-purged condition, the thermal conductance and resultant temperature stability is better than those in high-vacuum condition.</li>
</ol>

The authors have nothing to disclose.

In both WS2 NTs and flakes, we have successfully controlled the electric properties by electrostatic or electro chemical carrier doping.
In electrostatic doping region, ambipolar transistor operation has been observed. Such ambipolar transfer curve with a high on/off ratio (&#62;102) observed in low bias voltage indicates the effective carrier doping at the interface of electrolyte gating technique for tuning the Fermi level of these systems.
A...

Control of the carrier number is the key technique for realizing the quantum phase transition in solids1. In the conventional field effect transistor (FET), it is achieved by use of the solid gate1,2. In such a device, electric potential gradient is uniform throughout the dielectric materials so that induced carrier number at the interface is limited, shown in Figure 1a.
On the other hand, we can achieve the higher carrier density at the interface or bulk by replacing the solid dielectric materials with ionic gels/liquids or polymer electrolytes3,4,5,6,7,8,9,10,11 (Figure 1b). In the electrostatic doping by use of the ionic liquid, electric double layer transistor (EDLT) structure is formed at the interface between ionic liquid and sample, generating strong electric field (&#62;0.5 V/&#197;) even at low bias voltage. Resultant high carrier density (&#62;1014 cm-2) induced at the interface10,12,13 cause the novel electronic properties or quantum phase transition such as electric-field-induced ferromagnetism14, Coulomb blockade15, ambipolar transport16,17,18,19,20,21,22,23,24,25,26,27, formation of p-n junction and resultant electroluminance28,29,30, large modulation of thermoelectric powers31,32, charge density wave and Mott transitions33,34,35, and electric-field-induced insulator-metal transition36,37 including electric-field-induced superconductivity9,10,11,38,39,40,41,42,43,44,45,46,47,48,49.
In the electrolyte gating (Figure 1c), ions are not only accumulated at the interface to form EDLT, but can be also intercalated into layers of two-dimensional materials via thermal diffusion without damaging sample under applying the large gate voltage, leading to the electrochemical doping8,9,11,34,38,50,51,52,53. Thus, we can drastically change the carrier number compared to the conventional field effect transistor using the solid gate. In particular, the electric-field-induced superconductivity9,11,34,38,50 is realized by use of electrolyte gating in region of large carrier number where we cannot access by the conventional solid gating method.
In this article, we introduce this unique technique of carrier number control in solids and overview the transistor operation and electric-field-induced superconductivity in semiconducting WS2 samples such as WS2 flakes and WS2 nanotubes54,55,56,57.

<table><tbody><tr><td>Sonication machine</td><td>SND Co., Ltd.</td><td>US-2</td><td>http://www.senjyou.jp/</td></tr><tr><td>Spin-coater machine</td><td>ACTIVE Co.,Ltd.</td><td>ACT-300AII</td><td>http://www.acti-ve.co.jp/spincoater/standard/act300a2.html</td></tr><tr><td>Hot-plate</td><td>TAIYO</td><td>HP131224</td><td>http://www.taiyo-kabu.co.jp/products/detail.php?product_id=431</td></tr><tr><td>Optical Microscopy</td><td>OLYMPUS</td><td>BX51</td><td>https://www.olympus-ims.com/ja/microscope/bx51p/</td></tr><tr><td>Electron Beam Lithography machine</td><td>ELIONIX INC.</td><td>ELS-7500I</td><td>https://www.elionix.co.jp/index.html</td></tr><tr><td>Scribing machine</td><td>TOKYO SEIMITSU CO., LTD.</td><td>A-WS-100A</td><td>http://www.accretech.jp/english/product/semicon/wms/aws100s.html</td></tr><tr><td>Wire-bonding machine</td><td>WEST&amp;middot;BOND&amp;nbsp;</td><td>7476D-79</td><td>https://www.hisol.jp/products/bonder/wire/mgb/b.html</td></tr><tr><td>Physical Properties Measurement System</td><td>Quantum Design</td><td>PPMS</td><td>http://www.qdusa.com/products/ppms.html</td></tr><tr><td>Lock-in amplifier</td><td>Stanford Research Systems</td><td>SRS830</td><td>http://www.thinksrs.com/products/SR810830.htm</td></tr><tr><td>Source meter</td><td>Textronix</td><td>KEITHLEY 2612A</td><td>http://www.tek.com/keithley-source-measure-units/smu-2600b-series-sourcemeter</td></tr><tr><td>KClO&lt;sub&gt;4&lt;/sub&gt;</td><td>Sigma-Aldrich</td><td>241830</td><td>http://www.sigmaaldrich.com/catalog/product/sigald/241830?lang=ja&amp;amp;region=JP</td></tr><tr><td>PEG</td><td>WAKO</td><td>168-09075</td><td>http://www.siyaku.com/uh/Shs.do?dspCode=W01W0116-0907</td></tr><tr><td>IPA</td><td>WAKO</td><td>169-28121</td><td>http://www.siyaku.com/uh/Shs.do?dspWkfcode=169-28121</td></tr><tr><td>MIBK</td><td>WAKO</td><td>131-05645</td><td>http://www.siyaku.com/uh/Shs.do?dspCode=W01W0113-0564</td></tr><tr><td>PMMA</td><td>MicroChem</td><td>PMMA</td><td>http://microchem.com/Prod-PMMA.htm</td></tr><tr><td>Acetone</td><td>WAKO</td><td>012-26821</td><td>http://www.siyaku.com/uh/Shs.do?dspWkfcode=012-26821</td></tr></tbody></table>

electric-field control of electronic states in ws2 nanodevices by electrolyte gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape method or individual WS2 nanotubes by dispersing the suspension of WS2 nanotubes. The selected samples have been fabricated into devices by the use of the electron beam lithography and electrolyte is put on the devices. We have characterized the electronic properties of the devices under applying the gate voltage. In the small gate voltage region, ions in the electrolyte are accumulated on the surface of the samples which leads to the large electric potential drop and resultant electrostatic carrier doping at the interface. Ambipolar transfer curve has been observed in this electrostatic doping region. When the gate voltage is further increased, we met another drastic increase of source-drain current which implies that ions are intercalated into layers of WS2 and electrochemical carrier doping is realized. In such electrochemical doping region, superconductivity has been observed. The focused technique provides a powerful strategy for achieving the electric-filed-induced quantum phase transition.

The typical transistor operations of an individual WS2 NT and a WS2 flake devices are shown in Figure 3a and 3b, respectively, where the source drain current (IDS) as a function of the gate voltage (VG) nicely operates in an ambipolar mode, showing a remarkable contrast to the unipolar gate response by the conventional solid gated FET in previous publication58</su...

Watch this Scientific Journal Video about Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating at JoVE.com

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape ...

electric-field-control-electronic-states-ws2-nanodevices-electrolyte

Research

Education

JoVE Core

JoVE Journal

Physics

Engineering

Unit 1

Electric Charges and Fields

SCIENTISTS IN ACTION

11.3K Views.  The University of Tokyo. Here, we present a protocol to control the carrier number in solids by using the electrolyte.

Video: Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Fine-tuning the Size and Minimizing the Noise of Solid-state Nanopores

Solid-state nanopores have emerged as a versatile tool for the characterization of single biomolecules such as nucleic acids and proteins1. However, the creation of a nanopore in a thin insulating membrane remains challenging. Fabrication methods involving specialized focused electron beam systems can produce well-defined nanopores, but yield of reliable and low-noise nanopores in commercially available membranes remains low2,3 and size control is nontrivial4,5. Here, the application of high electric fields to fine-tune the size of the nanopore while ensuring optimal low-noise performance is demonstrated. These short pulses of high electric field are used to produce a pristine electrical signal and allow for enlarging of nanopores with subnanometer precision upon prolonged exposure. This method is performed in situ in an aqueous environment using standard laboratory equipment, improving the yield and reproducibility of solid-state nanopore fabrication.

A methodology for preparing solid-state nanopores in solution for biomolecular translocation experiments is presented. By applying short pulses of high electric fields, the nanopore diameter can be controllably enlarged with subnanometer precision and its electrical noise characteristics significantly improved. This procedure is performed in situ using standard laboratory equipment under experimental conditions.

Solid-state nanopores have emerged as a versatile tool for the characterization of single biomolecules such as nucleic acids and proteins1. However, the ...

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene&#8217;s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene&#39;s electronic structure in the presence of a charged impurity.&#160;The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene&#8217;s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices.

This paper details the fabrication process of a gate-tunable graphene device, decorated with Coulomb impurities for scanning tunneling microscopy studies. Mapping the spatially dependent electronic structure of graphene in the presence of charged impurities unveils the unique behavior of its relativistic charge carriers in response to a local Coulomb potential.

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengineering

Characterizing Electron Transport through Living Biofilms

Here we demonstrate the method of electrochemical gating used to characterize electrical conductivity of electrode-grown microbial biofilms under physiologically relevant conditions.1 These measurements are performed on living biofilms in aqueous medium using source and drain electrodes patterned on a glass surface in a specialized configuration referred to as an interdigitated electrode (IDA) array. A biofilm is grown that extends across the gap connecting the source and drain. Potentials are applied to the electrodes (ES and ED) generating a source-drain current (ISD) through the biofilm between the electrodes. The dependency of electrical conductivity on gate potential (the average of the source and drain potentials, EG = [ED + ES]/2) is determined by systematically changing the gate potential and measuring the resulting source-drain current. The dependency of conductivity on gate potential provides mechanistic information about the extracellular electron transport process underlying the electrical conductivity of the specific biofilm under investigation. The electrochemical gating measurement method described here is based directly on that used by M. S. Wrighton2,3 and colleagues and R. W. Murray4,5,6 and colleagues in the 1980&#39;s to investigate thin film conductive polymers.

A protocol for measuring electrical conductivity of living microbial biofilms under physiologically relevant conditions is presented.

Here we demonstrate the method of electrochemical gating used to characterize electrical conductivity of electrode-grown microbial biofilms under ...

Chemistry

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

Generation and Control of Electrohydrodynamic Flows in Aqueous Electrolyte Solutions

To drive electrohydrodynamic (EHD) flows in aqueous solutions, the separation of cation and anion transport pathways is essential because a directed electric body force has to be induced by ionic motions in liquid. On the other hand, positive and negative charges attract each other, and electroneutrality is maintained everywhere in equilibrium conditions. Furthermore, an increase in an applied voltage has to be suppressed to avoid water electrolysis, which causes the solutions to become unstable. Usually, EHD flows can be induced in non-aqueous solutions by applying extremely high voltages, such as tens of kV, to inject electrical charges. In this study, two methods are introduced to generate EHD flows induced by electrical charge separations in aqueous solutions, where two liquid phases are separated by an ion-exchange membrane. Due to a difference in the ionic mobility in the membrane, ion concentration polarization is induced between both sides of the membrane. In this study, we demonstrate two methods. (i) The relaxation of ion concentration gradients occurs via a flow channel that penetrates an ion-exchange membrane, where the transport of the slower species in the membrane selectively becomes dominant in the flow channel. This is a driving force to generate an EHD flow in the liquid. (ii) A long waiting time for the diffusion of ions passing through the ion-exchange membrane enables the generation of an ion-dragged flow by externally applying an electric field. Ions concentrated in a flow channel of a 1 x 1 mm2 cross-section determine the direction of the liquid flow, corresponding to the electrophoretic transport pathways. In both methods, the electric voltage difference required for an EHD flow generation is drastically reduced to near 2 V by rectifying the ion transport pathways.

The rectification of ion transport pathways is an effective method to generate one-directional ion-dragged electrohydrodynamic flows. By setting an ion-exchange membrane in a flow channel, an electrically polarized condition is generated and causes a liquid flow to be driven when an electric field is externally applied.

To drive electrohydrodynamic (EHD) flows in aqueous solutions, the separation of cation and anion transport pathways is essential because a directed ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Preparation of Silicon Nanowire Field-effect Transistor for Chemical and Biosensing Applications

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we describe the preparation of polycrystalline silicon nanowire field-effect transistors (pSNWFETs) that serve as biosensing devices for biomarker detection. A protocol for chemical and biomolecular sensing by using pSNWFETs is presented. The pSNWFET device was demonstrated to be a promising transducer for real-time, label-free, and ultra-high-sensitivity biosensing applications. The source/drain channel conductivity of a pSNWFET is sensitive to changes in the environment around its silicon nanowire (SNW) surface. Thus, by immobilizing probes on the SNW surface, the pSNWFET can be used to detect various biotargets ranging from small molecules (dopamine) to macromolecules (DNA and proteins). Immobilizing a bioprobe on the SNW surface, which is a multistep procedure, is vital for determining the specificity of the biosensor. It is essential that every step of the immobilization procedure is correctly performed. We verified surface modifications by directly observing the shift in the electric properties of the pSNWFET following each modification step. Additionally, X-ray photoelectron spectroscopy was used to examine the surface composition following each modification. Finally, we demonstrated DNA sensing on the pSNWFET. This protocol provides step-by-step procedures for verifying bioprobe immobilization and subsequent DNA biosensing application.

We describe key steps for biosensing by using polysilicon nanowire field-effect transistors, including the preparation of the device and the immobilization and confirmation of a DNA molecular probe on the nanowire surface, as well as conditions for DNA sensing.

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we ...

Electric-field Control of Electronic States in WS₂ Nanodevices by Electrolyte Gating

Podsumowanie

Przeglądaj więcej filmów

PLAYLIST