シリコン上のエピタキシャルナノ構造α-クオーツフィルム:材料から新しいデバイスへ

Nowadays, quartz-based sensors are limited by the miniaturization process and the monolithic integration of this material on silicon. These bottlenecks are now overcome with the first chemical integration of epitaxial requirements in the form of high quality microcantilevers. From a technological perspective, this novel quartz devices open the door to the development of cost effective active microelectromechanical system ingenerate from lead-free piezoelectric oxide materials and providing high forces and mass sensitivity while preserving its quality factor.

Begin by mixing one part of the curing agent with 10 parts of elastomer in a beaker on the balance. Stir this mixture with a glass stick until a homogenous distribution of air bubbles is obtained, then fill the master with PDMS and remove the bubbles in a vacuum chamber. Introduce the PDMS and silicon master into a stove at 70 degrees Celsius for two hours.

Replicate the silicon master using the PDMS solution as described in the manuscript. Prepare two by six centimeter sized substrates by cutting a two inch P-type SOI wafer in a direction parallel or perpendicular to the wafer flat using a diamond tip, ensuring that the conductivity of the silicon device layer is between 1 and 10 ohms per centimeter. To eliminate possible fabrication polymers, introduce these substrates into a piranha solution for 20 minutes.

Hang the prepared SOI substrate from the dip coder arm, place a beaker underneath it and fill it with strontium-based solution. In order to obtain a homogeneous silica film, set the dip coder's chamber to 40%relative humidity and 25 degrees Celsius. Adjust the dip coding sequence to a speed of 300 millimeters per minute at the immersion and withdrawal and start the dip process at 40%relative humidity.

After dip coating, introduce the SOI substrate into a furnace at 450 degrees Celsius for five minutes to consolidate the gel film to a thickness of 200 nanometers. Repeat the dip coating twice to produce a film with approximately 600 nanometer thickness. Start a new dip coating and place the prepared PDMS mold on the SOI substrate.

Put the apparatus in the furnace at 70 degrees Celsius for one minute and then at 140 degrees Celsius for two minutes. Remove the PDMS mold to obtain a micro or nanostructured gel film on the SOI substrate and then place the SOI substrate in the furnace at 450 degrees Celsius for five minutes to consolidate the pattern gel film height to 600 nanometers. Place the sample in a ceramic boat and introduce it into the furnace at 1, 000 degrees Celsius for five hours.

Cover the furnace and saturate it with air. When finished, allow the furnace to cool to room temperature without any programmed ramp. For patterning a cantilever shape on the quartz thin film, begin by putting the samples inside the piranha solution to clean all organic residues, then place them on a hot plate at 140 degrees Celsius for 10 minutes of dehumidification.

Spin AZ 2070 negative photoresist at a speed of 4, 000 rotations per minute for 30 seconds, then put the sample on the hot plate to soft bake it at 115 degrees Celsius for 60 seconds. Expose the sample to an ultraviolet dose of 37.5 millijoules per square centimeter for five seconds and put the sample on the hot plate again for a post-exposure bake. Develop the sample in metal-ion free 726 developer for 100 seconds at ambient temperature.

Rinse it with deionized water and dry with nitrogen. Expect a thickness of 5.5 micrometers. Put the sample on the hot plate at 125 degrees Celsius for 10 minutes to hard bake the photoresist.

Using a reactive ion etching system, etch the quartz to the silicon layer with the gas flow rate and radiofrequency power settings described in the text manuscript. Clean it with plasma at a flow rate of 90 standard cubic centimeters per minute of oxygen for five minutes. For realization of the bottom and top electrode, spin AZ 2020 negative photoresist and perform a soft bake as previously described.

Expose the sample to an ultraviolet dose of 23.25 milligrams per square centimeter for three seconds and put it on the hot plate for a post-exposure bake. Develop, rinse, and blow dry the sample as described in the text manuscript. Expect a thickness of 1.7 micrometers.

Deposit 50 nanometers of chromium metal and 120 nanometers of platinum metal at a rate of four ampere per second and 2.5 ampere per second respectively with electron beam evaporation at 10 to the negative six millibars. Leave the samples in acetone first and then in isopropyl alcohol until metal liftoff is successful. For patterning the sample to etch the silicon 100 layer, spin AZ 2070 negative photoresist at a speed of 2, 000 rotations per minute for 30 seconds and put the sample on the hot plate for a soft bake at 115 degrees Celsius for 60 seconds.

Expose the sample to an ultraviolet dose of 37.5 millijoules per square centimeter for five seconds and put the sample on the hot plate again for a post-exposure bake. Develop, rinse, and dry the sample as described in the text manuscript. Expect a thickness of 5.9 micrometers.

Put the sample on a hot plate at 125 degrees Celsius for 10 minutes to hard bake the photoresist. Using a reactive ion etching system, etch the silicon layer to the silicon dioxide layer with gas flow rate and radiofrequency power settings described in the text manuscript. To release the cantilever by wet chemical etching, spin AZ 2020 negative photoresist at a speed of 2, 000 rotations per minute for 30 seconds and put the sample on a hot plate for a soft bake at 115 degrees Celsius for 60 seconds.

Expose the sample to an ultraviolet dose of 37.5 millijoules per square centimeter for five seconds and put the sample on the hot plate again for a post-exposure bake. Develop, rinse, and dry the sample as described in the text manuscript. Expect a thickness of 2.3 micrometers.

Put the sample on the hot plate at 125 degrees Celsius for 10 minutes to hard bake the resist. Put buffered oxide etch solution in a polytetrafluoroethylene-based container and leave the sample in the solution at ambient temperature until all silicon oxide layers are etched under the cantilever. Clean the sample carefully with water and remove the resin with acetone and IPA.

The synthesis and nanostructuration steps of quartz films and microfabrication of quartz cantilever were depicted schematically by monitoring different steps with real images. The aspects of a nanostructured quartz-based chip with different cantilever dimensions and its cross-sectional image on the SOI substrate are shown here. 2D micro x-ray diffraction controlled the crystallinity of the different stacking layers of the cantilever.

Their thicknesses are indicated in the diffractogram. The detailed crystallization of quartz pillars was analyzed using the electron diffraction technique and FEGSEM images in the back-scattered electrons mode. A deeper structural characterization of a single quartz-based piezoelectric nanostructured cantilever was performed by recording the pole figure and rocking curve.

The electromechanical response of the quartz-based piezoelectric cantilevers was detected using a laser Doppler vibrometer and with an atomic force microscope. The linear dependence of the cantilever amplitude and applied AC voltage was recorded with the optical beam deflection system of the atomic force microscope. The most important thing about this process is to ensure sequestered quality of the quartz, its functionality on this mechanical quality factor.

For that, three things are necessary. First, it's mandatory to protect etch quartz layer to avoid any acid infiltration during the release of the cantilever. The second thing is to use buffer solution which permit a gentle release.

And the last one is to increase the thickness of the negative photoresist which permit a longer wet etch time. This process offer major advantages over quartz in term of size, power consumption, and integration cost. It will facilitate the future fabrication of single-chip solution for multi-frequency devices while preserving miniaturization and cost effective processes.