This work was supported by the National Science Council, Taiwan under contract No. MOST 105-2112-M-003-016-MY3. This work was also in part supported by the National Nano Device Laboratories and e-beam laboratory in electrical engineering of National Taiwan University.

1. 2D Quasi-heterojunction Transistors Fabrication Process
<ol>
	<li>Prepare commercial c-plane sapphire.
	<ol>
		<li>Wash the whole single-side polished sapphire (2-inch) with acetone.</li>
		<li>Rinse the sapphire substrate with isopropyl alcohol.</li>
	</ol>
	</li>
	<li>Grow MoS2 on sapphire substrate using CVD in a hot-wall furnace.
	<ol>
		<li>Place 0.6 g of molybdenum trioxide (MoO3) powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the MoO3 powder.</li>
		<li>Prepare sulfur (S) powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 190 &#176;C during the reaction.</li>
		<li>Use argon (Ar = 70 sccm, 40 Torr) gas flow to bring the S and MoO3 vapors to the sapphire substrate while heating the center zone to 750 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 750 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Perform EBL. 
	NOTE: A thin Au of about 5 nm was deposited by the sputtering for discharging during all EBL processes on sapphire substrate
	<ol>
		<li>Identify, using an optical microscope, an area where MoS2 monolayer flakes are observed, then design the stripe pattern layout for that specific area using a design software (AutoCAD).</li>
		<li>Spin-coat photoresist (PR), for example polymethyl methacrylate (PMMA) or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.3.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the lines in the layout. 
		NOTE: For line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply post-exposure bake (PEB) on the sample after the exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use tetramethylammonium hydroxide (TMAH) 2.38% as developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL of deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Define the stripe structures using 50 W oxygen (O2) plasma etching (1st etching) for 30 s to 2 min and remove PR using 50 mL of acetone.</li>
	<li>Grow tungsten diselenide (WSe2) using CVD on the target location, which will result in a preferred growth of WSe2 layer between the already existing MoS2 stripes on the sapphire substrate.
	<ol>
		<li>Place 0.6 g of tungsten trioxide (WO3) powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the WO3 powder.</li>
		<li>Prepare selenium (Se) powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 260 &#176;C during the reaction.</li>
		<li>Use Ar/H2 (Ar = 90 sccm, H2 = 6 sccm, 20 Torr) gas flow to bring the Se and WO3 vapors to the sapphire substrate while heating the center zone to 925 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 925 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Fabricate the metal pad arrays and alignment marks.
	<ol>
		<li>Overlay the patterns of metal pad arrays and alignment the marks using photolithography patterning technique.</li>
		<li>Deposit 20 nm/60 nm Ti/Au using electron gun evaporator. 
		NOTE: Gold is used to avoid the oxidization of the metal pads.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process via optical microscopy until the metal pads become apparent.</li>
	</ol>
	</li>
	<li>Perform another EBL process to overlay a ribbon shape pattern on top of the MoS2-WSe2 heterojunction.
	<ol>
		<li>Measure the coordinate displacement between the target locations in the MoS2-WSe2 heterojunction and the alignment marks using optical microscopy and design the ribbon-shape layout based on these measurements using a software (AutoCAD).</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.7.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the lines in the layout. 
		NOTE: For line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the position of the alignment marks in the sapphire substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Use O2 plasma etching (2nd etching) to define a ribbon-shaped lateral heterojunction, and remove PR by acetone.</li>
	<li>Perform the EBL process to overlay the pattern of the Ti/Au metal electrodes.
	<ol>
		<li>Measure the coordinate displacement between the target locations in the MoS2-WSe2 heterojunction and the alignment marks using optical microscopy and design the metal electrode layout based on these measurements using a software (AutoCAD).</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.9.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the metal lines in the layout. 
		NOTE: For metal line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the positions of the alignment marks in the sapphire substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Perform Ti/Au Metal Deposition and Lift-off
	<ol>
		<li>Deposit Ti/Au metal using electron gun evaporator with the thickness of less than 100 nm, otherwise, it will be difficult to remove the PR and the unwanted metal by lift-off.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process via optical microscopy until there are only metal lines and pads left.</li>
	</ol>
	</li>
	<li>Perform the EBL process in step 1.9 but overlay the Pd/Au metal electrode&#39;s pattern instead of Ti/Au.</li>
	<li>Perform the metal deposition and lift-off process in step 1.10 but deposit Pd/Au instead of Ti/Au.</li>
</ol>
2. 2D Back-gated Transistors Fabrication Process
<ol>
	<li>Prepare back-gated Si/SiO2 substrates with alignment marks.
	<ol>
		<li>Prepare homemade or commercial SiO2/Si substrate.</li>
		<li>Use photolithography or EBL patterning techniques to define the alignment mark.</li>
		<li>Perform reactive ion etching (RIE) on the SiO2/Si substrate until the total depth of the target area reaches 1000 nm and remove the PR by O2 plasma to reveal the formed alignment marks.</li>
		<li>Overlay the patterns of metal pad arrays using photolithography patterning technique.</li>
		<li>Deposit 20 nm/60 nm Ti/Au using electron gun evaporator. 
		NOTE: Gold is used to avoid oxidization of the metal pads.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process by optical microscopy until the metal pads become apparent.</li>
	</ol>
	</li>
	<li>Perform CVD of MoS2 on sapphire substrate in a hot-wall furnace.
	<ol>
		<li>Place 0.6 g of MoO3 powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the MoO3 powder.</li>
		<li>Prepare S powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 190 &#176;C during the reaction.</li>
		<li>Use argon (Ar = 70 sccm, 40 Torr) gas flow to bring the S and MoO3 vapors to the sapphire substrate while heating the center zone to 750 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 750 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Transfer MoS2 from the sapphire to the back-gated SiO2/Si substrate.
	<ol>
		<li>Spin coat PMMA with the spin speed of 3500 rpm for 30 s on top of the MoS2 film.</li>
		<li>Bake the MoS2/sapphire sample at 120 &#176;C for 3 min in order to strengthen the PMMA coating.</li>
		<li>Dip the MoS2/Sapphire sample into 50 mL of ammonia solution (14.5%) for around 30 min to 2 h to separate the MoS2 film from the sapphire substrate.</li>
		<li>Pick up the film and transfer it to the SiO2/Si substrate.</li>
		<li>Bake the MoS2/SiO2/Si sample in order to enhance the adhesion between the MoS2 and SiO2 layers. Heat the sample at 120 &#176;C for around 30 min to 1 h.</li>
		<li>Remove the PMMA by washing it with 30 mL of acetone for around 30 min to 2 h.</li>
		<li>Rinse the sample with isopropyl alcohol and use nitrogen to blow it dry.</li>
	</ol>
	</li>
	<li>Perform EBL. 
	NOTE: There is no thin Au deposited on SiO2/Si substrate during EBL process since Si is somehow conductive.
	<ol>
		<li>Measure the coordinate displacement between the target locations and the alignment marks using optical microscopy and, based on these measurements, design the pattern layout of the metal electrodes using a design software. 
		NOTE: Metal electrodes connect the target points in the MoS2 sample to the metal pads in the SiO2/Si substrate.</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 2.4.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the metal lines in the layout. 
		NOTE: For metal line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the position of the alignment marks in the Si/SiO2 substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after the exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL of deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Perform Au Metal Deposition and Lift-off
	<ol>
		<li>Deposit Au metal using electron gun evaporator with the thickness of less than 100 nm, otherwise, it will be difficult to remove the PR and the unwanted metal by lift-off.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the process via optical microscopy until there are only metal lines and pads left.</li>
	</ol>
	</li>
</ol>

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The authors have nothing to disclose.

In this article, the detailed procedures of fabricating novel electronics based on 2D materials in nanometer scale are demonstrated. Since the sample preparation procedures of each application have differences with each other, the overlapped processes were treated as the protocol. Electron beam patterning combined with material location determination and metal electrode definition thus serves as the protocol here. Among the two types of devices mentioned, the whole process of 2D back-gated transistors starting at wet tra...

Since past decades, mankind has been experiencing rapid downscale in the size of transistors and, consequently, an exponential increase in the number of transistors in integrated circuits (ICs). This maintains the continuous progress of silicon-based complementary metal-oxide semiconductor (CMOS) technology1. Moreover, this current trend in the size and performance of fabricated devices are still on-track with Moore&#39;s law, which states that the number of transistors on electronic chips, as well as their performance, doubles roughly every two years2. CMOS transistors are present in most, if not all, of the electronic devices available in the market and thus making it an integral part of human lives. Due to this, there are continuous demands for improvements in chip size and performance which have been pushing the manufacturers to keep following the Moore&#39;s law track.
Unfortunately, Moore&#39;s law appears to be nearing its end due to the amount of heat generated as more silicon circuitry is squeezed into a small area2. This calls for new types of materials that can provide the same, if not better, performance as silicon and, at the same time, can be implemented in a relatively smaller scale. Recently, new promising materials have been subjects of many material science researches. Such materials as one-dimensional (1D) carbon nanotubes3,4,5,6,7, 2D graphene8,9,10,11,12, and transition metal dichalcogenides (TMDs)13,14,15,16,17,18, are good candidates that can be used as substitute for the silicon-based CMOS and continue the Moore&#39;s law track.
Fabrication of small-scale devices requires careful determination of the material&#39;s location to successfully proceed to the other fabrication techniques such as lithography and metal electrode definition. So, the method presented in this paper was designed to address this need. Compared to the traditional semiconductor fabrication techniques19, the approach presented in this paper is tailor-fitted to the development of small-scale devices which needs more attention in terms of finding the location of the material. The aim of this method is to reliably fabricate 2D nanomaterial devices, such as 2D back-gated transistors and Q-HBTs, using standard fabrication processes. This can serve as a platform for future nanodevice developments as it paves the way towards the production of future advanced nano-scale devices.
In the proceeding section, the fabrication processes for 2D materials-based devices namely, the Q-HBT and 2D back-gated transistor are discussed in detail. Electron beam patterning combined with material location determination and metal electrode definition comprises the protocol since they are required in both mentioned processes. Part 1 discusses the step-by-step fabrication process of Q-HBTs20; and part 2 demonstrates a universal approach to obtain chemical vapor deposition (CVD) molybdenum disulfide (MoS2) back-gated transistors from transfer to lift-off21, which has been completely shown in the article. The detailed process flow is illustrated in (Figure 1).

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a standard and reliable method to fabricate two-dimensional nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The device fabrication processes have been applied to several of the corresponding author&#39;s researches involving the development of 2D material devices. In this part, the results of some of these researches are presented to demonstrate the effectivity of the protocol discussed above. A monolayer of lateral WSe2-MoS2 Q-HBT20 is selected as the first example. Using the standard device fabrication processes detailed in the protocol, the monol...

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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

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Research

JoVE Journal

Engineering

9.5K Views.  National Taiwan Normal University. Het artikel beoogt de invoering van een standaard en betrouwbare fabricage-procedure voor de ontwikkeling van toekomstige lage dimensionale nano-elektronica.

Video: A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Chemistry

A Method to Fabricate Disconnected Silver Nanostructures in 3D

The standard nanofabrication toolkit includes techniques primarily aimed at creating 2D patterns in dielectric media. Creating metal patterns on a submicron scale requires a combination of nanofabrication tools and several material processing steps. For example, steps to create planar metal structures using ultraviolet photolithography and electron-beam lithography can include sample exposure, sample development, metal deposition, and metal liftoff. To create 3D metal structures, the sequence is repeated multiple times. The complexity and difficulty of stacking and aligning multiple layers limits practical implementations of 3D metal structuring using standard nanofabrication tools. Femtosecond-laser direct-writing has emerged as a pre-eminent technique for 3D nanofabrication.1,2 Femtosecond lasers are frequently used to create 3D patterns in polymers and glasses.3-7 However, 3D metal direct-writing remains a challenge. Here, we describe a method to fabricate silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm. The method enables the fabrication of patterns not feasible using other techniques, such as 3D arrays of disconnected silver voxels.8 Disconnected 3D metal patterns are useful for metamaterials where unit cells are not in contact with each other,9 such as coupled metal dot10,11or coupled metal rod12,13 resonators. Potential applications include negative index metamaterials, invisibility cloaks, and perfect lenses.
In femtosecond-laser direct-writing, the laser wavelength is chosen such that photons are not linearly absorbed in the target medium. When the laser pulse duration is compressed to the femtosecond time scale and the radiation is tightly focused inside the target, the extremely high intensity induces nonlinear absorption. Multiple photons are absorbed simultaneously to cause electronic transitions that lead to material modification within the focused region. Using this approach, one can form structures in the bulk of a material rather than on its surface.
Most work on 3D direct metal writing has focused on creating self-supported metal structures.14-16 The method described here yields sub-micrometer silver structures that do not need to be self-supported because they are embedded inside a matrix. A doped polymer matrix is prepared using a mixture of silver nitrate (AgNO3), polyvinylpyrrolidone (PVP) and water (H2O). Samples are then patterned by irradiation with an 11-MHz femtosecond laser producing 50-fs pulses. During irradiation, photoreduction of silver ions is induced through nonlinear absorption, creating an aggregate of silver nanoparticles in the focal region. Using this approach we create silver patterns embedded in a doped PVP matrix. Adding 3D translation of the sample extends the patterning to three dimensions.

Femtosecond-laser direct-writing is frequently used to create three-dimensional (3D) patterns in polymers and glasses. However, patterning metals in 3D remains a challenge. We describe a method for fabricating silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm.

The standard nanofabrication toolkit includes  techniques primarily aimed at creating 2D patterns in dielectric media. Creating  metal patterns on a ...

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

Atomically Traceable Nanostructure Fabrication

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process being used in order to maintain exquisite control over both feature size and feature density. Here, we demonstrate a method for tracking atomically resolved and controlled structures from initial template definition through final nanostructure metrology, opening up a pathway for top-down atomic control over nanofabrication. Hydrogen depassivation lithography is the first step of the nanoscale fabrication process followed by selective atomic layer deposition of up to 2.8 nm of titania to make a nanoscale etch mask. Contrast with the background is shown, indicating different mechanisms for growth on the desired patterns and on the H passivated background. The patterns are then transferred into the bulk using reactive ion etching to form 20 nm tall nanostructures with linewidths down to ~6 nm. To illustrate the limitations of this process, arrays of holes and lines are fabricated. The various nanofabrication process steps are performed at disparate locations, so process integration is discussed. Related issues are discussed including using fiducial marks for finding nanostructures on a macroscopic sample and protecting the chemically reactive patterned Si(100)-H surface against degradation due to atmospheric exposure.

We report a protocol for combining the atomic metrology of the Scanning Tunneling Microscope for surface patterning with selective Atomic Layer Deposition and Reactive Ion Etching. Using a robust process involving numerous atmospheric exposures and transport, 3D nanostructures with atomic metrology are fabricated.

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process ...

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengineering

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape method or individual WS2 nanotubes by dispersing the suspension of WS2 nanotubes. The selected samples have been fabricated into devices by the use of the electron beam lithography and electrolyte is put on the devices. We have characterized the electronic properties of the devices under applying the gate voltage. In the small gate voltage region, ions in the electrolyte are accumulated on the surface of the samples which leads to the large electric potential drop and resultant electrostatic carrier doping at the interface. Ambipolar transfer curve has been observed in this electrostatic doping region. When the gate voltage is further increased, we met another drastic increase of source-drain current which implies that ions are intercalated into layers of WS2 and electrochemical carrier doping is realized. In such electrochemical doping region, superconductivity has been observed. The focused technique provides a powerful strategy for achieving the electric-filed-induced quantum phase transition.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

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