Name: flow-assisted dielectrophoresis: a low cost method for the fabrication of high performance solution-processable nanowire devices
Uploaded: 2017-12-07T14:00:00.000+00:00
Duration: 9 min 14 s
Description: Watch this Scientific Journal Video about Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices at JoVE.com

The authors would like to thank ESPRC and BAE systems for financial support, and Prof. Brian A. Korgel and his group for the supply of SFLS grown silicon nanowires used in this work.

Caution: All procedures unless otherwise stated take place in a clean room environment and risk assessments have been done to ensure safety during nanowires and chemicals handling. Nanomaterials may have a number of health implications which are as of yet unknown, and so should be handled with appropriate care21.
NOTE: The process starts with the preparation of the substrates, followed by the first photolithography and metal deposition steps to define the DEP contacts. The nanowires are then assembled via DEP and a further optional photolithographic and metal deposition step can be performed to deposit top contacts onto nanowires. The nanowire transistor devices current-voltage characteristics are then measured using a semiconductor characterization kit.
1. Preparation of Substrates
<ol>
	<li>Cut a doped n-type silicon/silicon dioxide wafer into suitable sizes, e.g., 2.5 cm2.</li>
	<li>During cutting, ensure the top surface of the wafer is not touched or scratched.</li>
	<li>Run a diamond scriber across the surface in one continuous motion to make a cut.</li>
	<li>Split the wafer along the cut.</li>
	<li>Place the samples on a substrate holder and sonicate for 5 min in an ultra-sonic bath at 100% power (450 W), first in deionized water, then acetone, and finally isopropanol (IPA). 
	NOTE: See Table of Materials for CAS numbers and suppliers.</li>
	<li>Dry the substrates with a nitrogen gun to remove any remaining IPA or dust from the surface.</li>
	<li>Plasma ash the samples in oxygen plasma at 100 W for 5 min to remove any remaining organic residues.</li>
</ol>
2. Photolithography Bilayer Process for Contacts
NOTE: A bilayer photolithography process is used to create electrodes. The photolithography process is conducted in a yellow room to prevent decay of photoresist materials.
<ol>
	<li>Heat the sample at 150 &#176;C for 15 min using a hotplate, to remove any remaining water from the surface. 
	NOTE: This is to ensure adhesion of photoresist; however chemical primers such as HMDS may also be used.</li>
	<li>Remove the sample from the hot plate and place it on a spin-coater.</li>
	<li>Using a&#160;pipette, drop approximately 1 mL of photoresist A on the surface until the entire sample is uniformly covered. 
	NOTE: See Table of Materials for the exact photoresist used.</li>
	<li>Spin the sample at 4,000 rpm for 45 s, to produce a film thickness of approximately 250 nm. If electrodes that are thicker than 150 nm are to be deposited, change this recipe.</li>
	<li>Remove the sample from the spin-coater and place it on a hotplate at 150 &#176;C for 5 min.</li>
	<li>Remove the sample from the hotplate and leave the sample to rest for 5 min in a 50% humidity box. This is to ensure rehydration of the photoresist22. 
	NOTE: If the humidity of the lab is greater than 50%, the sample may be left to rest in the air.</li>
	<li>Place the sample back onto the spin-coater and pipette approximately 1 mL of photoresist B on the surface of the substrate.</li>
	<li>Spin the sample at 3,500 rpm for 45 s, giving a film thickness of approximately 500 nm.</li>
	<li>Place the sample on a hotplate at 120 &#176;C for 2 min.</li>
	<li>Remove the sample from the hotplate and leave to rest in a 50% humidity box for 5 min.</li>
	<li>Expose the sample using a mask-aligner and photomask to UV light for 6.7 s for a total of 180 mJ of exposure. 
	NOTE: The exact exposure dose might need to be adjusted depending on a particular model of mask aligner.</li>
	<li>Remove the sample from the mask-aligner and develop by immersing it in photoresist developer&#160;for 30 s. 
	NOTE: See Table of Materials for the exact developer.</li>
	<li>Remove the sample from the developer, immerse the sample into deionized water, and rinse it to stop the development process.</li>
	<li>Check the photolithography using an optical microscope. A polarizer can be used to check the bilayer undercut which should appear as faint lines around the channel. The time may be adjusted if too much or two little undercut is achieved.</li>
</ol>
3. Deposition of Metal Contacts
NOTE: Electron beam (E-beam) deposition is used to deposit electrodes onto the prepared photoresist. This process can also use thermal evaporators or other types of metal thin film deposition techniques.
<ol>
	<li>Place the samples in the E-beam chamber; pump it down until a high vacuum is reached. In this case, a vacuum of around 1 x 10-6 mTorr is reached.</li>
	<li>Deposit 2 - 6 nm of titanium which acts as an adhesion layer followed by 30 nm of gold for the DEP contacts.</li>
	<li>Remove the samples from the E-beam chamber.</li>
	<li>Perform the lift-off procedure by removing most of the photoresist and excess metal. This is done by placing the samples into a beaker of photoresist remover for 15 min.</li>
	<li>Remove the samples from the beaker of photoresist remover A and place into another clean beaker of photoresist remover&#160;for a further 15 min. This is to prevent any large metal particles from settling on the sample.</li>
	<li>Complete lift-off by sonicating the beaker for 5 min at 50% power.</li>
	<li>Remove the samples from the bath one-by-one, ensuring to rinse off any material with IPA to prevent undesired metal particles from settling between electrodes. 
	NOTE: The electrodes are now prepared for the DEP alignment of nanowires.</li>
</ol>
4. DEP of Nanowires
<ol>
	<li>Prepare a solution of silicon or other nanowires in anisole of approximately 1 &#181;g/mL concentration. In this experiment, the solution is briefly sonicated for 15 s at the lowest power setting possible to remove any flocculation. Other solvents can be used such as toluene and N,N-dimethylformamide (DMF)1.</li>
	<li>Check the solution by drop casting a 10 &#181;L of the nanowire formulation onto a sacrificial substrate.</li>
	<li>Inspect the substrate with deposited nanowires using a polarized optical microscope (POM). The silicon nanowires are birefringent and hence can be easily seen in POM. If there are no nanowire clumps visible, and most of nanowires are well dispersed on the substrate, then the next stage can begin, otherwise the solution is re-sonicated, and the nanowire concentration might need to be adjusted. It may take several attempts to achieve the correct nanowire dispersion.</li>
	<li>Place the prepared sample with electrodes onto 30&#176; (vs. horizon) inclined platform with the device channel aligned horizontally. The dispersion flow direction needs to be perpendicular to the electrodes edges to allow more efficient nanowire alignment.</li>
	<li>Contact the electrodes using micro-probes connected to a frequency generator1.</li>
	<li>Set the desired frequency and voltage are on the frequency generator. In this experiment, use a DEP signal voltage of 10 V peak-to-peak and a 1 MHz sinewave. 
	NOTE: Increasing the frequency up to 20 MHz can help to collect nanowires with high conductivity and low trap density1,2. See reference1 for a detailed discussion. DEP signal frequency range indicated here was obtained by conducting SFLS Si nanowires impedance spectroscopy and collection time analysis, as described in reference1. Other types of nanowires with higher or lower charge carrier mobility, doped nanowires, or nanowires obtained by other growth methods can have different DEP signal frequency range resulting in the collection of high quality nanowires.</li>
	<li>Switch-on the frequency generator and drop approximately 10 &#181;L of nanowire solution using a micropipette onto the device area. 
	NOTE: Placing the sample at an angle (30&#176;) helps to create a gravity-assisted slow flow of the liquid. Alternatively, a capillary action using a glass slide can be used6.</li>
	<li>Apply the DEP signal for 30 s and then switch-off the frequency generator.</li>
	<li>Remove the sample and rinse very gently with IPA.</li>
	<li>Dry-off the sample very gently using a nitrogen gun. A polarized optical microscope may be used to inspect the sample and adjust parameters 
	NOTE: The DEP signal voltage, frequency, and the nanowire dispersion density can be adjusted to achieve a reproducible desired density of nanowires, from a few nanowires to a few hundred per device1,2.</li>
</ol>
5. Deposition of a Secondary Metal Layer
<ol>
	<li>To achieve improved current injection in NW FETs, apply a second metallic contact on top of the nanowire. 
	NOTE: This contact deposition process follows the exact same steps as sections 2 and 3, in both photolithography and metal deposition, except that only a gold layer is deposited.</li>
</ol>
6. I-V Characterization of Nanowire Devices
NOTE: The samples are now complete and can be used in subsequent experiments or their I-V characteristics can be measured to establish nanowire FET electrical properties. The fabricated devices are back-gated FETs, where doped silicon wafer serves as the common gate, and SiO2 layer serves as the gate dielectric.
<ol>
	<li>To establish electrical contact with the gate, remove a small area of the silicon oxide at the edge of the sample using a diamond scriber.</li>
	<li>Use a nitrogen gun to remove any undesired silicon dioxide particles.</li>
	<li>Place three microprobes (source, drain, and gate) on the gold source-drain electrode contacts, with the gate probe on the area with removed SiO2.</li>
	<li>Use a semiconductor characterization system to take I-V measurements.</li>
	<li>Measure transfer and output scans of NW FETs as these give information on the performance of the device and the electrical properties of the nanowires1,17,23. Note that transfer measurements involve stepping source-drain voltage and sweeping gate voltage. The output characteristics are measured by sweeping source-drain voltage and stepping gate voltage.</li>
</ol>

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The authors confirm that there are no conflicts of interest.

The successful fabrication and performance of the devices depend on several key factors. These include nanowire density and distribution in the formulation, the choice of solvent, the frequency of DEP, and the control of the number of nanowires present on the device electrodes1.
One of the critical steps in achieving repeatable working devices is the preparation of a nanowire formulation without clusters or clumps. The formulation can be sonicated before DEP to reduce t...

Controllable and reproducible assembly of nanoparticles in pre-defined substrate locations is one of the main challenges in solution-processed electronic and photonic devices utilizing semiconducting or conducting nanoparticles. For high performance devices, it is also highly beneficial to be able to select nanoparticles with preferential sizes, and particular electronic properties, including, for example, high conductivity and low density of surface trap states. Despite significant progress in nanomaterials growth, including nanowire and nanotube materials, some variations of nanoparticle properties are always present, and a selection step can significantly improve nanoparticle-based device performance1,2.
The purpose of the flow-assisted DEP method demonstrated in this work is to address the above challenges by showing controllable semiconducting nanowires assembly onto metallic contacts for high performance nanowire field effect transistors. DEP solves several problems of nanowire device fabrication in a single step including positioning of nanowires, alignment/orientation of nanowires, and selection of nanowires with desired properties via DEP signal frequency selection1. DEP has been used for numerous other devices ranging from gas sensors3, transistors1, and RF switches4,5, to the positioning of bacteria for analysis7.
DEP is the manipulation of polarizable particles via the application of a non-uniform electric field resulting in nanowires self-assembly across the electrodes8. The method was originally developed for the manipulation of bacteria9,10 but has since been expanded to the manipulation of nanowires and nanomaterials.
DEP solution processing of nanoparticles enables semiconductor device fabrication that significantly differs from traditional top-down techniques based on multiple photomasking, ion implantation, high temperature14, annealing, and etching steps. Since DEP manipulates nanoparticles that have already been synthesized, it is a low-temperature, bottom-up fabrication technique11. This approach allows large-scale nanowire devices to be assembled on almost any substrate including temperature-sensitive, flexible plastic substrates6,12,13.
In this work, high performance p-type silicon nanowire field effect transistors are fabricated using flow-assisted DEP, and the FET current-voltage characterization is conducted. The silicon nanowires used in this work are grown via the Super Fluid Liquid Solid (SFLS) method15,16. The nanowires are intentionally&#160;doped, and are approximately 10 - 50 &#181;m in length and 30 - 40 nm in diameter. The SFLS growth method is very attractive since it can offer industry scalable amounts of nanowire materials15. The proposed nanowire assembly methodology is directly applicable to other semiconductor nanowire materials such as InAs13, SnO23, and GaN18. The technique can also be expanded to align conductive nanowires19 and to position nanoparticles across electrode gaps20.

<table><tbody><tr><td>Silicon/silicon dioxide wafer, CZ method growth, 100mm diameter,&amp;nbsp; 300 nm oxide thermal growth,&amp;nbsp; n-doped phosphorus</td><td>Si-Mat (Silicon materials)</td><td>-</td><td>http://si-mat.com/</td></tr><tr><td>Acetone (200ml)</td><td>Sigma Aldrich</td><td>W332615</td><td>-</td></tr><tr><td>Isopropanol (200ml)</td><td>Sigma Aldrich</td><td>W292907</td><td>-</td></tr><tr><td>Deionised water (150ml)</td><td>On site supply</td><td>-</td><td>-</td></tr><tr><td>Photoresist (A) SF6 PMGI under etch photoresit (approx 1 ml per sample)</td><td>Microchem&amp;nbsp;</td><td>-</td><td>http://microchem.com/pdf/PMGI-Resists-data-sheetV-rhcedit-102206.pdf</td></tr><tr><td>Photoresist (B) S1805 photoresit) (approx 1 ml per sample)</td><td>Microchem&amp;nbsp;</td><td>-</td><td>http://www.microchem.com/PDFs_Dow/S1800.pdf</td></tr><tr><td>Photoresist developer Microposit&amp;nbsp; MF319&amp;nbsp; (100ml)</td><td>Microchem&amp;nbsp;</td><td>-</td><td>http://microchem.com/products/images/uploads/MF_319_Data_Sheet.pdf</td></tr><tr><td>Photoresist remover Microposit remover 1165 (300ml (2 baths 150 each))</td><td>Microchem&amp;nbsp;</td><td>-</td><td>http://micromaterialstech.com/wp-content/dow_electronic_materials/datasheets/1165_Remover.pdf</td></tr></tbody></table>

flow-assisted dielectrophoresis: a low cost method for the fabrication of high performance solution-processable nanowire devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

Bilayer photolithography results in clean sharply defined electrodes. In the example (Figure 1A), inter-digitated finger structure was used with a channel length of 10 &#181;m. These structures allow a large area to assemble the maximum number of nanowires when the DEP force is applied. Figure 1B shows a schematic of a bottom-gate nanowire FET device.
Incorrect nanowire...

Watch this Scientific Journal Video about Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices at JoVE.com

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

flow-assisted-dielectrophoresis-low-cost-method-for-fabrication-high

Research

JoVE Journal

Engineering

7.6K Views.  University of Surrey. In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Video: Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Chemistry

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms.
In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station.

A detailed procedure for surface doping of Silicon interfaces is provided. The ultra-shallow surface doping is demonstrated by using phosphorus containing monolayers and rapid annealing process. The method can be used for doping of macroscopic area surfaces as well as nanostructures.

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra ...

Evaluating Plasmonic Transport in Current-carrying Silver Nanowires

Plasmonics is an emerging technology capable of simultaneously transporting a plasmonic signal and an electronic signal on the same information support1,2,3. In this context, metal nanowires are especially desirable for realizing dense routing networks4. A prerequisite to operate such shared nanowire-based platform relies on our ability to electrically contact individual metal nanowires and efficiently excite surface plasmon polaritons5 in this information support. In this article, we describe a protocol to bring electrical terminals to chemically-synthesized silver nanowires6 randomly distributed on a glass substrate7. The positions of the nanowire ends with respect to predefined landmarks are precisely located using standard optical transmission microscopy before encapsulation in an electron-sensitive resist. Trenches representing the electrode layout are subsequently designed by electron-beam lithography. Metal electrodes are then fabricated by thermally evaporating a Cr/Au layer followed by a chemical lift-off. The contacted silver nanowires are finally transferred to a leakage radiation microscope for surface plasmon excitation and characterization8,9. Surface plasmons are launched in the nanowires by focusing a near infrared laser beam on a diffraction-limited spot overlapping one nanowire extremity5,9. For sufficiently large nanowires, the surface plasmon mode leaks into the glass substrate9,10. This leakage radiation is readily detected, imaged, and analyzed in the different conjugate planes in leakage radiation microscopy9,11. The electrical terminals do not affect the plasmon propagation. However, a current-induced morphological deterioration of the nanowire drastically degrades the flow of surface plasmons. The combination of surface plasmon leakage radiation microscopy with a simultaneous analysis of the nanowire electrical transport characteristics reveals the intrinsic limitations of such plasmonic circuitry.

Silver nanowires can simultaneously transport electrons and optical information in the form of surface plasmons. A procedure is described here to realize such a shared circuitry and the limitations at propagating both information carriers are evaluated.

Plasmonics is an emerging technology capable of simultaneously transporting a plasmonic signal and an electronic signal on the same information ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengineering

Creating Sub-50 Nm Nanofluidic Junctions in PDMS Microfluidic Chip via Self-Assembly Process of Colloidal Particles

Polydimethylsiloxane (PDMS) is the prevailing building material to make microfluidic devices due to its ease of molding and bonding as well as its transparency. Due to the softness of the PDMS material, however, it is challenging to use PDMS for building nanochannels. The channels tend to collapse easily during plasma bonding. In this paper, we present an evaporation-driven self-assembly method of silica colloidal nanoparticles to create nanofluidic junctions with sub-50 nm pores between two microchannels. The pore size as well as the surface charge of the nanofluidic junction is tunable simply by changing the colloidal silica bead size and surface functionalization outside of the assembled microfluidic device in a vial before the self-assembly process. Using the self-assembly of nanoparticles with a bead size of 300 nm, 500 nm, and 900 nm, it was possible to fabricate a porous membrane with a pore size of ~45 nm, ~75 nm and ~135 nm, respectively. Under electrical potential, this nanoporous membrane initiated ion concentration polarization (ICP) acting as a cation-selective membrane to concentrate DNA by ~1,700 times within 15 min. This non-lithographic nanofabrication process opens up a new opportunity to build a tunable nanofluidic junction for the study of nanoscale transport processes of ions and molecules inside a PDMS microfluidic chip.

We propose a simple self-assembly technique of silica colloidal nanoparticles to create a nanofluidic junction between two microchannels in polydimethylsiloxane (PDMS). Using this technique, a nanoporous bead membrane with a pore size down to ~45 nm was built inside a microchannel and applied to electrokinetic preconcentration of DNA samples.

Polydimethylsiloxane (PDMS) is the prevailing building material to make microfluidic devices due to its ease of molding and bonding as well as its ...

Fabrication of Fully Solution Processed Inorganic Nanocrystal Photovoltaic Devices

We demonstrate a method for the preparation of fully solution processed inorganic solar cells from a spin and spray coating deposition of nanocrystal inks. For the photoactive absorber layer, colloidal CdTe and CdSe nanocrystals (3-5 nm) are synthesized using an inert hot injection technique and cleaned with precipitations to remove excess starting reagents. Similarly, gold nanocrystals (3-5 nm) are synthesized under ambient conditions and dissolved in organic solvents. In addition, precursor solutions for transparent conductive indium tin oxide (ITO) films are prepared from solutions of indium and tin salts paired with a reactive oxidizer. Layer-by-layer, these solutions are deposited onto a glass substrate following annealing (200-400 &#176;C) to build the nanocrystal solar cell (glass/ITO/CdSe/CdTe/Au). Pre-annealing ligand exchange is required for CdSe and CdTe nanocrystals where films are dipped in NH4Cl:methanol to replace long-chain native ligands with small inorganic Cl- anions. NH4Cl(s) was found to act as a catalyst for the sintering reaction (as a non-toxic alternative to the conventional CdCl2(s) treatment) leading to grain growth (136&#177;39 nm) during heating. The thickness and roughness of the prepared films are characterized with SEM and optical profilometry. FTIR is used to determine the degree of ligand exchange prior to sintering, and XRD is used to verify the crystallinity and phase of each material. UV/Vis spectra show high visible light transmission through the ITO layer and a red shift in the absorbance of the cadmium chalcogenide nanocrystals after thermal annealing. Current-voltage curves of completed devices are measured under simulated one sun illumination. Small differences in deposition techniques and reagents employed during ligand exchange have been shown to have a profound influence on the device properties. Here, we examine the effects of chemical (sintering and ligand exchange agents) and physical treatments (solution concentration, spray-pressure, annealing time and annealing temperature) on photovoltaic device performance.

This protocol describes the synthesis and solution deposition of inorganic nanocrystals layer by layer to produce thin film electronics on non-conductive surfaces. Solvent-stabilized inks can produce complete photovoltaic devices on glass substrates via spin and spray coating following post-deposition ligand exchange and sintering.

We demonstrate a method for the preparation of fully solution processed inorganic solar cells from a spin and spray coating deposition of nanocrystal ...

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape method or individual WS2 nanotubes by dispersing the suspension of WS2 nanotubes. The selected samples have been fabricated into devices by the use of the electron beam lithography and electrolyte is put on the devices. We have characterized the electronic properties of the devices under applying the gate voltage. In the small gate voltage region, ions in the electrolyte are accumulated on the surface of the samples which leads to the large electric potential drop and resultant electrostatic carrier doping at the interface. Ambipolar transfer curve has been observed in this electrostatic doping region. When the gate voltage is further increased, we met another drastic increase of source-drain current which implies that ions are intercalated into layers of WS2 and electrochemical carrier doping is realized. In such electrochemical doping region, superconductivity has been observed. The focused technique provides a powerful strategy for achieving the electric-filed-induced quantum phase transition.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Iron Nanowire Fabrication by Nano-Porous Anodized Aluminum and its Characterization

Magnetic nanowires possess unique properties that have attracted the interest of different fields of research, including basic physics, biomedicine, and data storage. We demonstrate a fabrication method for iron (Fe) nanowires&#160;via electrochemical deposition into anodic&#160;alumina oxide (AAO) templates. The templates are fabricated by anodization of aluminum (Al) discs, and the pore length and diameter are controlled by changing the anodizing conditions. Pores with an average diameter of around 120 nm are created using oxalic acid as the electrolyte. Using this method, cylindrical nanowires are synthesized, which are released by dissolving the alumina using a selective chemical etchant.

In this work, we describe a&#160;protocol to fabricate iron nanowires, including the formation of the porous alumina membrane that is used as the template, electrodeposition into templates using electrolyte solution, and the release of the nanowires into the solution.

Magnetic nanowires possess unique properties that have attracted the interest of different fields of research, including basic physics, biomedicine, and ...