The authors acknowledge financial support from EPSRC, grant MQIC.

NOTE: Semiconductor heterostructure and hybrid S-Sm Josephson junction fabrication are&#160;presented.
1. Semiconducting heterostructure fabrication
NOTE: The molecular beam epitaxy (MBE) grown In0.75Ga0.25As quantum wells are used in this study23,24,25,26. Figure 1 depicts the sequence of distinct layers:
<ol>
	<li>Clean a 500 &#956;m thick, 3-inch semi-insulating (001) GaAs substrate and remove the oxide layer in high temperature (above 200 &#176;C)26.</li>
	<li>Adjust the growth temperature at 580 &#176;C and grow the buffer layer of GaAs/AlAs/GaAs films with thicknesses of 50/75/250 nm26.</li>
	<li>Ramp down the substrate temperature for 20 min and then grow a step-graded buffer layer of InAlAs with a 1300 nm thickness at starting substrate temperatures of T = 416, 390, 360, 341, 331 and 337 &#176;C26.</li>
	<li>Grow a 30 nm thick In0.75Ga0.25As quantum well 2DEG at slightly higher substrate temperature26.</li>
	<li>Cover the 2DEG quantum well with a 60 nm In0.75Al0.25As spacer, and then modulation dope the wafer by a 15 nm thick of a n-type In0.75Al0.25As. This will assure the conductance in the dark26.</li>
	<li>Grow a 45 nm In0.75Al0.25As layer followed by a cap layer of InGaAs with thickness of 2 nm26.</li>
	<li>Perform the measurement of the Shubnikov&#8211;de Haas oscillations and Hall effect to find the electron density (ns) and mobility (&#956;e) at temperature T= 1.5 K26. From the transport measurements, it was inferred that the ns= 2.24&#215;1011 (cm-2) and &#956;e= 2.5&#215;105 (cm2/Vs) in the dark but ns= 2.28&#215;1011 (cm-2) and &#956;e= 2.58&#215;105 (cm2/Vs) after illumination.</li>
</ol>
2. Two-dimensional Josephson junction fabrication
NOTE: Here, the fabrication process of the hybrid QICs with two different approaches are discussed23,24,25. Device 1 with eight identical long Josephson junctions was fabricated only with a few steps of photolithography processing. The second device fabrication procedure was similar to device 1 up to formation of JJs which step the e-beam- lithography was used.
<ol>
	<li>Sketch the JJs and QIC device layout, including mesa and ohmic patterns by using AutoCad software25. Start the drawing by selecting appropriate layers to form the layer selector menu. Create a new layer from Format | Layer in the AutoCad software.</li>
	<li>Design and fabricate the photolithography mask. Choose desired shapes and geometries from the panel menu in the software. Click on the desired shape of JJs (i.e., rectangles, squares) and push the drawing window to initiate the shape (click in the Autocad software help menu for more details).</li>
	<li>Pattern the JJs and QICs designs, after developing the photoresist on the wafer, and fabricate the mesa structures to act as the active region (the raised area in Figure 1) by wet-etch in acid solutions of H2SO4: H2O2: (1:8:1000)23,24,25. Rinse the device in DI water for 30 s and then dry with nitrogen gas.</li>
	<li>Ensure an etch depth of ~&#160;150 nm by the DEKTAK surface profiler23,24,25.</li>
	<li>Form ohmic contacts, to make electrical contact between the metal and 2DEG, by spinning photoresist on top of the wafer and then exposure to UV light through a photo-mask. Develop the resist in MF-319 for 1 min. Deposit a thin layer, between 50 nm and 100 nm of gold/germanium/nickel (AuGeNi) alloy over the resist-patterned sample23,24,25.</li>
	<li>Etch a &#8275; 140 nm deep trench on top of the active region to form 2D JJs by either photolithographically (device 1) or e- beam lithographically (device 2) patterning and wet-etching in acid described above (the JJs should be formed far from the ohmic contacts, a distance of &#62; 100 &#956;m, to ensure that the normal electrons from this part do not influence to the junction&#8217;s interfaces)23,24,25.</li>
	<li>Sputter a &#8275;130 nm superconducting Nb film to form Nb-In0.75Ga0.25As-Nb JJs (by DC magnetron sputtering in Ar plasma),</li>
	<li>Deposit 10/50 nm thick Ti/Au films for electrical contacts and transport measurement purposes.</li>
	<li>Transfer and load the device on the standard leadless chip carrier (LCC) by using GE varnish, and make the electrical contacts between the device and LCC pads by using gold wires.</li>
	<li>Load the devices into a 3He cryostat or dilution refrigerator for transport measurements.</li>
</ol>

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The authors have nothing to disclose.

On-chip QICs comprising an array of JJs based on superconducting indium gallium arsenide (In0.75Ga0.25As) quantum wells were demonstrated. Two important challenges of hybrid S-Sm material systems such as the scalability and interface transparency were addressed. Two critical steps whining the protocol including the growth of high quality and high mobility In0.75Ga0.25As two-dimensional electron gas in semiconducting heterostructures and proximity induced superconductivity into 2DEG were discussed23,24,25.
Growth of In0.75Ga0.25As with step-graded buffer layers in GaAs substrate and also the formation of homogeneous and barrier-free interfaces between the superconductor and semiconductor is a crucial step in such hybrid 2D quantum circuit development. It was demonstrated that with careful etching the sputtered superconducting film can make highly transparent contacts to In0.75Ga0.25As quantum wells resulting in detection of induced superconducting gap in semiconductors23,24,25.
The significance with respect to existing methods is that the presented technique for 2D hybrid JJs and circuit realization does not require the insitu deposition of superconductor on semiconductors in an MBE chamber after the semiconductor growth has been completed23,24,25. The other significance is that the heterostructure wafer can be grown as a desk of up to 10 cm diameter, allowing the fabrication of thousands of hybrid 2D junctions and circuits, so overcoming the scalability challenges of the hybrid S-Sm quantum circuits and devices22,23,24,25.
The induced superconductivity in quantum wells, SGS on differential conductance of the 2D junctions, and the phase coherent ballistic quantum transport measured in our junctions strongly suggest that hybrid 2D junctions and circuits based on superconducting In0.75Ga0.25As 2DEG afford promising material system for scalable quantum processing and computing technologies. Our approach may open a new road toward quantum technology and helps pave the way for the development of on-chip topological quantum circuits for realizing the next generation of quantum processors23,24,25.

A Josephson junction (JJ) is formed by sandwiching a thin layer of a non-superconducting (normal) material between two superconductors1. Various novel quantum electronic and photonic circuits and devices can be built based on JJs2,3,4,5,6,7,8,9,10,11,12,13,14,15,16. Among them, the JJs with semiconductor as their non-superconducting (normal) part, or superconductor-semiconductor-superconductor (S-Sm-S) JJs, have received much attention in recent years after the purported detection of exotic Majorana particles with zero electrical charges at the interface of a superconductor and a semiconducting one-dimensional (1D) nanowire17,18,19,20,21,22. Nanowire-based hybrid devices are limited to the 1D geometry of the nanowire and fabrication of Y and/or T-structures out of them - a necessary requirement for Majorana braiding- is challenging22. The fine tuning of nanowire&#8217;s chemical potential, for accessing topological phases, requires JJs with several electrostatically gates which causes quite a lot of issues in complex device fabrication out of nanowires. To overcome the scalability issues of 1D wires, two-dimensional (2D) material platforms are highly desirable19,22.
Among 2D materials, the two-dimensional electron gas (2DEG) platform -forms when electrons are confined to an interface between two different materials in a semiconductor heterostructure- is the most promising candidate22. The combination of 2DEG with superconductors and forming hybrid 2D JJs opens a new avenue towards the development of next-generation scalable quantum systems such as topological quantum processing and computing. They can support phase coherent quantum transport, and proximity induced superconductivity with high transmission probability, which are fundamental requirement for topological phase observation. In this regard, we demonstrate a QIC on a chip which consists of array of ballistic 2D JJs that can be controlled by 20 wires. Each junction has two Nb electrodes as the superconducting part and In0.75Ga0.25As quantum wells in a semiconducting heterojunction as the normal part. The wafer can be easily patterned to form complex structures and networked QICs.
The advantages of In0.75Ga0.25As 2DEG include: (i) relatively large g-factor, (ii) strong Rashba spin-orbit coupling, (iii) the low electron effective mass, and (iv) that the indium composition can be tuned allowing the formation of JJs with high interface transparency23,24,25. The wafer can be grown as a disk of up to 10 cm dimeter, allowing fabrication of thousands of hybrid 2D JJs and complex QICs networks so overcoming the scalability challenges of these quantum devices.
We discuss two different approaches for device fabrications: For device 1, a circuit which includes eight identical and symmetric JJs of 850 nm length and 4 &#956;m widths are patterned by photolithography23,24. The device 2 includes eight junctions with different lengths. They all have the same width of 3 &#956;m. The JJs are patterned by e-bam lithography25. The transport measurements at sub-Kelvin temperature ranges in absence/presence of magnetic field will be presented. The on-chip QICs consists of array of 2D Nb- In0.75Ga0.25As -Nb JJs. The long and short junctions are measured in a dilution fridge with a base temperature of 40 mK and liquid 3He cooled cryostat with a base temperature of 300 mK, respectively. Devices are biased with an ac-signal of 5 &#956;V at 70 Hz which is superimposed to the junction dc voltage bias. A two-terminal standard lock-in technique is used to measure the device output ac-current23,24,25.

<table><tbody><tr><td>CompactDAQ Chassis</td><td>National Instruments</td><td>NI cDAC-9178</td><td></td></tr><tr><td>DSP Lock-in Amplifier</td><td>AMETEK 7265</td><td>190284-A-MNL-C</td><td></td></tr><tr><td>Dilution refrigerator</td><td>Blueforce</td><td></td><td>Buttom loaded fridge</td></tr><tr><td>Dilution refrigerator</td><td>Oxford</td><td>KelvinoxMX40</td><td>Wet-fridge</td></tr><tr><td>Diamond scriber MICROTEC</td><td>Karl Suss</td><td>HR 100</td><td></td></tr><tr><td>Dektak Surface Profilometer</td><td>Veeco</td><td>3ST</td><td></td></tr><tr><td>Evaporator</td><td>Edwards</td><td>AUTO 306</td><td></td></tr><tr><td>Evaporator</td><td>Edwards</td><td>Coating system E306A</td><td></td></tr><tr><td>&lt;sup&gt;3&lt;/sup&gt;He Cryostat</td><td>Oxford</td><td></td><td></td></tr><tr><td>&amp;nbsp;Photoresist Spinner</td><td>Headway Research Inc.</td><td>&amp;nbsp;EC101DT-R790&amp;nbsp;</td><td></td></tr><tr><td>Matlab</td><td></td><td></td><td></td></tr><tr><td>Mask Aligner</td><td>Karl Suss</td><td>MJB 3</td><td></td></tr><tr><td>Source meter</td><td>Keithley&amp;nbsp;</td><td>2614B</td><td></td></tr><tr><td>Semiconducting heterostructure</td><td>MBE Veeco&amp;nbsp;</td><td>Gen III system</td><td>MBE Grown wafers</td></tr><tr><td>Wire Bonder</td><td>K&amp;amp;S&amp;nbsp;</td><td>4524</td><td></td></tr></tbody></table>

scalable quantum integrated circuits on superconducting two-dimensional electron gas platform

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface between two different materials is necessary. The S-Sm junction with high interface transparency will then facilitate the observation of the induced hard superconducting gap, which is the key requirement to access the topological phases (TPs) and observation of exotic quasiparticles such as Majorana zero modes (MZM) in hybrid systems. A material platform that can support observation of TPs and allows the realization of complex and branched geometries is therefore highly demanding in quantum processing and computing science and technology. Here, we introduce a two-dimensional material system and study the proximity induced superconductivity in semiconducting two-dimensional electron gas (2DEG) that is the basis of a hybrid quantum integrated circuit (QIC). The 2DEG is a 30 nm thick In0.75Ga0.25As quantum well that is buried between two In0.75Al0.25As barriers in a heterostructure. Niobium (Nb) films are used as the superconducting electrodes to form Nb- In0.75Ga0.25As -Nb Josephson junctions (JJs) that are symmetric, planar and ballistic. Two different approaches were used to form the JJs and QICs. The long junctions were fabricated photolithographically, but e-beam lithography was used for short junctions&#8217; fabrication. The coherent quantum transport measurements as a function of temperature in the presence/absence of magnetic field B are discussed. In both device fabrication approaches, the proximity induced superconducting properties were observed in the In0.75Ga0.25As 2DEG. It was found that e-beam lithographically patterned JJs of shorter lengths result in observation of induced superconducting gap at much higher temperature ranges. The results that are reproducible and clean suggesting that the hybrid 2D JJs and QICs based on In0.75Ga0.25As quantum wells could be a promising material platform to realize the real complex and scalable electronic and photonic quantum circuitry and devices.

Figure 2a shows the scanning electron microscope (SEM) image of the device 1. A quantum circuit with 20 electrical wires can be seen. The design allows the measurement of one or series of JJs on a chip in one fridge cool-down. The SEM image of one junction on the circuit of Device 2, that was fabricated by e-beam lithography, is shown in Figure 2b. The distance between two Nb films in each side of the Nb-In0.75Ga0.25As-Nb junction is L= 550 nm at the shortest path. Figure 2c shows the SEM image of one junction of Device 1- which is photolithographically fabricated. Here, the two Nb electrodes are separated by a distance of L= 850 nm.
The Blonder&#8211;Tinkham&#8211;Klapwijk (BTK) theory is an acceptable model to describe the quantum transport in hybrid S-Sm junctions27. The influence of the superconductor order parameters in semiconducting 2DEG results in a nonlinear differential conductance. At low temperatures, there are two possible reflection mechanisms at the Nb-In0.75Ga0.25As interfaces: normal reflection which causes no charge transmission through the interface and the Andreev reflections, which transmits two charge quanta 2e, with the retroreflection of a hole23,24,25. As the superconducting condensate consists of spin singlet Cooper pairs, the reflected hole has the opposite spin as the incoming electron. The cartoon diagram of these two processes is shown in Figure 3a,b, respectively28.
If the interface between the Nb and In0.75Ga0.25As contact is not transparent, there is coexistence of both normal and Andreev reflected electrons. Thus, the resistance increases and a zero-bias peak within the gap is formed. Such an in-gap peak in the dV/dI (VSD) is not observed in our junctions. However, for a homogeneous and barrier free (Z=0) interface between the Nb film and In0.75Ga0.25As contact, all incident electrons undergo Andreev reflection. In such condition, an excess current Iexc is formed in the junction due to correlations of electron- and hole-like quasiparticles. Therefore, the differential resistance within the gap is reduced and a flat U-shape dip in dV/dI (VSD) is observed. According to BTK model, it can be inferred that no tunneling barrier formed at the Nb-In0.75Ga0.25As interfaces of both devices. Therefore, the barrier strength is estimated to be Z &#60; 0.2 in our junctions23,24,25.
Because of the proximity effect, induced gap of approximately &#916;ind &#8776; 100 &#956;eV, and 650 &#956;eV are measured in the devices 1 and 2, respectively. The temperature dependence induced superconducting gap with pronounced subharmonic energy gap structures (SGS) peaks and dips for device 1 are shown in Figure 4a. The multiple Andreev reflections (MAR) at the interfaces of the Nb-In0.75Ga0.25As junction result in the observation of SGS in the differential conductance. At the lowest measured temperature T= 50 mK (red curve), the SGS appears with three peaks (named as P1, P2 and P3) and three dips (named as d1, d2 and d3). The temperature evolution of the peaks and dips due to the suppression of the induced superconductivity with temperature increase are shown in Figure 4b. The SGS peak positions obey the expression V = 2&#916;/ne (&#916; is the Nb gap energy, n = 1, 2, 3, &#8230; is an integer, and e is the electron charge): P1, P2, P3 and P4 positions approximately correspond to 2&#916;/3e, 2&#916;/4e, 2&#916;/6e and the induced gap edge but the dip positions do not follow the expression. All features are significantly temperature dependent, and the strongest (weakest) SGS peaks (dips) are observed at T= 50 mK (800 mK). It is worth mentioning that even at temperatures above T= 500 mK where the supercurrent can no longer be seen, the SGS is observed but it disappears at T&#62; 800 mK- when induced superconductivity is washed out.
For this device with array of eight 2D JJs, in 4 out of 7 junctions, a hard-induced superconducting gap in In0.75Ga0.25As 2DEG was found23,24. However, three junctions showed a soft gap signature and neither a hard- nor a soft-gap structure was observed for the last junction because of a wire contact failure between the device and pad.
The superconducting gap as a function of applied VSD voltage and temperature of device 2 is shown in Figure 5a. This device was measured at a 3He cryostat with base temperature of T= 280 mK. The temperature and magnetic field dependences transport measurements of device 2 do not show any sign of in-gap or sub-gap oscillations which are observed for device 1 (see Figure 5a, b). This could be due to the arrow-shaped geometry of the junction which may cause destructive interference of the MAR. Such features might appear in the differential conductance if the device is measured at much lower temperatures (dilution fridge base temperature). The induced gap is suppressed and moved toward zero voltage bias and their amplitudes diminish with further increasing of the applied temperature and magnetic field.
<img alt="Figure 1" class="xfigimg" src="/files/ftp_upload/57818/57818fig1.jpg" /> 
Figure 1. In0.75Ga0.25As/In0.75Al0.25As/GaAs heterostructure. The schematic view of the heterojunction where an In0.75Ga0.25As quantum well with 30 nm thickness is formed &#8275;120 nm below the wafer surface. Nb was used as the superconducting contacts (shown in black) to form a hybrid and ballistic Nb&#8211;In0.75Ga0.25As 2DEG&#8211;Nb Josephson junction. <a href="https://www.jove.com/files/ftp_upload/57818/57818fig1large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 2" class="xfigimg" src="/files/ftp_upload/57818/57818fig2.jpg" /> 
Figure 2: On-chip hybrid superconducting-semiconducting quantum circuits. (a) SEM image of the QICs device showing a top view of a quantum circuit with 20 control wires, and 8 planar and symmetric JJs on a chip. The SEM image of Nb-In0.75Ga0.25As-Nb JJs with an In0.75Ga0.25As 2DEG gap of length L= 550 nm and 850 nm for e-beam lithographically (b) and photolithographically (c) fabricated junctions. <a href="https://www.jove.com/files/ftp_upload/57818/57818fig2large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 3" class="xfigimg" src="/files/ftp_upload/57818/57818fig3.jpg" /> 
Figure 3. Normal and Andreev Reflections in hybrid superconducting-semiconducting junctions. (a) Specular quasiparticle reflection with no charge transmission through the interface. (b) Andreev reflection whereas the incoming electron is reflected as a hole in the opposite spin sub-band and transfer 2e charge into superconducting electrode. <a href="https://www.jove.com/files/ftp_upload/57818/57818fig3large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 4" class="xfigimg" src="/files/ftp_upload/57818/57818fig4.jpg" /> 
Figure 4. Induced superconductivity and SGS in In0.75Ga0.25As quantum wells in photolithographically fabricated junction. (a) Temperature dependence induced superconducting gap with pronounced SGS peaks due to multiple Andreev reflections. The SGS and the induced gap edge peaks, are marked by P1 to P4 while the SGS dips are marked by d1 to d3. (b) The SGS peaks and dips shown in (a) as a function of temperature. SGS are suppressed significantly at T&#62; 400 mK leading to a shift toward zero bias. <a href="https://www.jove.com/files/ftp_upload/57818/57818fig4large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 5" class="xfigimg" src="/files/ftp_upload/57818/57818fig5.jpg" /> 
Figure 5. The temperature and magnetic field dependence of induced superconductivity in e-beam lithographically fabricated junctions. (a) Induced superconducting gap vs. applied source-drain voltage VSD at temperatures between 300 mK and 1.5 K. The curves are vertically offset for clarity. (b) Color-coded differential resistance as a function of VSD and perpendicular magnetic field at T= 300 mK. <a href="https://www.jove.com/files/ftp_upload/57818/57818fig5large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>

Watch this Scientific Journal Video about Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform at JoVE.com

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Quantum integrated circuits (QICs) consisting of array of planar and ballistic Josephson junctions (JJs) based on In0.75Ga0.25As two-dimensional electron gas (2DEG) is demonstrated. Two different methods for fabrication of the two-dimensional (2D) JJs and QICs are discussed followed by the demonstration of quantum transport measurements in sub-Kelvin temperatures.

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface ...

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9.5K Views.  University of Cambridge. Quantum integrated circuits (QICs) consisting of array of planar and ballistic Josephson junctions (JJs) based on In0.75Ga0.25As two-dimensional electron gas (2DEG) is demonstrated. Two different methods for fabrication of the two-dimensional (2D) JJs and QICs are discussed followed by the demonstration of quantum transport measurements in sub-Kelvin temperatures.

Video: Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient echo memory (GEM) is a protocol for storing optical quantum states of light in atomic ensembles. The primary motivation for such a technology is that quantum key distribution (QKD), which uses Heisenberg uncertainty to guarantee security of cryptographic keys, is limited in transmission distance. The development of a quantum repeater is a possible path to extend QKD range, but a repeater will need a quantum memory. In our experiments we use a gas of rubidium 87 vapor that is contained in a warm gas cell. This makes the scheme particularly simple. It is also a highly versatile scheme that enables in-memory refinement of the stored state, such as frequency shifting and bandwidth manipulation. The basis of the GEM protocol is to absorb the light into an ensemble of atoms that has been prepared in a magnetic field gradient. The reversal of this gradient leads to rephasing of the atomic polarization and thus recall of the stored optical state. We will outline how we prepare the atoms and this gradient and also describe some of the pitfalls that need to be avoided, in particular four-wave mixing, which can give rise to optical gain.

The gradient echo memory is a protocol for storing optical quantum states of light in atomic ensembles. Quantum memory is a key element of a quantum repeater, which can extend the range of quantum key distribution. We outline the operation of the scheme when implemented in a 3-level atomic ensemble.

Gradient  echo memory (GEM) is a protocol for storing optical quantum states of light in  atomic ensembles. The primary motivation for such a technology ...

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene&#8217;s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene&#39;s electronic structure in the presence of a charged impurity.&#160;The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene&#8217;s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices.

This paper details the fabrication process of a gate-tunable graphene device, decorated with Coulomb impurities for scanning tunneling microscopy studies. Mapping the spatially dependent electronic structure of graphene in the presence of charged impurities unveils the unique behavior of its relativistic charge carriers in response to a local Coulomb potential.

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

Measurement of Quantum Interference in a Silicon Ring Resonator Photon Source

Silicon photonic chips have the potential to realize complex integrated quantum information processing circuits, including photon sources, qubit manipulation, and integrated single-photon detectors. Here, we present the key aspects of preparing and testing a silicon photonic quantum chip with an integrated photon source and two-photon interferometer. The most important aspect of an integrated quantum circuit is minimizing loss so that all of the generated photons are detected with the highest possible fidelity. Here, we describe how to perform low-loss edge coupling by using an ultra-high numerical aperture fiber to closely match the mode of the silicon waveguides. By using an optimized fusion splicing recipe, the UHNA fiber is seamlessly interfaced with a standard single-mode fiber. This low-loss coupling allows the measurement of high-fidelity photon production in an integrated silicon ring resonator and the subsequent two-photon interference of the produced photons in a closely integrated Mach-Zehnder interferometer. This paper describes the essential procedures for the preparation and characterization of high-performance and scalable silicon quantum photonic circuits.

Silicon photonic chips have the potential to realize complex integrated quantum systems. Presented here is a method for preparing and testing a silicon photonic chip for quantum measurements.

Silicon photonic chips have the potential to realize complex integrated quantum information processing circuits, including photon sources, qubit ...

Resonance Fluorescence of an InGaAs Quantum Dot in a Planar Cavity Using Orthogonal Excitation and Detection

The ability to perform simultaneous resonant excitation and fluorescence detection is important for quantum optical measurements of quantum dots (QDs). Resonant excitation without fluorescence detection &#8211; for example, a differential transmission measurement &#8211; can determine some properties of the emitting system, but does not allow applications or measurements based on the emitted photons. For example, the measurement of photon correlations, observation of the Mollow triplet, and realization of single photon sources all require collection of the fluorescence. Incoherent excitation with fluorescence detection &#8211; for example, above band-gap excitation &#8211; can be used to create single photon sources, but the disturbance of the environment due to the excitation reduces the indistinguishability of the photons. Single photon sources based on QDs will have to be resonantly excited to have high photon indistinguishability, and simultaneous collection of the photons will be necessary to make use of them. We demonstrate a method to resonantly excite a single QD embedded in a planar cavity by coupling the excitation beam into this cavity from the cleaved face of the sample while collecting the fluorescence along the sample&#39;s surface normal direction. By carefully matching the excitation beam to the waveguide mode of the cavity, the excitation light can couple into the cavity and interact with the QD. The scattered photons can couple to the Fabry-Perot mode of the cavity and escape in the surface normal direction. This method allows complete freedom in the detection polarization, but the excitation polarization is restricted by the propagation direction of the excitation beam. The fluorescence from the wetting layer provides a guide to align the collection path with respect to the excitation beam. The orthogonality of the excitation and detection modes enables resonant excitation of a single QD with negligible laser scattering background.

Resonant excitation of a single self-assembled quantum dot can be achieved using an excitation mode orthogonal to the fluorescence collection mode. We demonstrate a method using the waveguide and Fabry-Perot modes of a planar microcavity surrounding the quantum dots. The method allows complete freedom in the detection polarization.

The ability to perform simultaneous resonant excitation and fluorescence detection is important for quantum optical measurements of quantum dots (QDs). ...

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape method or individual WS2 nanotubes by dispersing the suspension of WS2 nanotubes. The selected samples have been fabricated into devices by the use of the electron beam lithography and electrolyte is put on the devices. We have characterized the electronic properties of the devices under applying the gate voltage. In the small gate voltage region, ions in the electrolyte are accumulated on the surface of the samples which leads to the large electric potential drop and resultant electrostatic carrier doping at the interface. Ambipolar transfer curve has been observed in this electrostatic doping region. When the gate voltage is further increased, we met another drastic increase of source-drain current which implies that ions are intercalated into layers of WS2 and electrochemical carrier doping is realized. In such electrochemical doping region, superconductivity has been observed. The focused technique provides a powerful strategy for achieving the electric-filed-induced quantum phase transition.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape ...

Generation and Coherent Control of Pulsed Quantum Frequency Combs

We present a method for the generation and coherent manipulation of pulsed quantum frequency combs. Until now, methods of preparing high-dimensional states on-chip in a practical way have remained elusive due to the increasing complexity of the quantum circuitry needed to prepare and process such states. Here, we outline how high-dimensional, frequency-bin entangled, two-photon states can be generated at a stable, high generation rate by using a nested-cavity, actively mode-locked excitation of a nonlinear micro-cavity. This technique is used to produce pulsed quantum frequency combs. Moreover, we present how the quantum states can be coherently manipulated using standard telecommunications components such as programmable filters and electro-optic modulators. In particular, we show in detail how to accomplish state characterization measurements such as density matrix reconstruction, coincidence detection, and single photon spectrum determination. The presented methods form an accessible, reconfigurable, and scalable foundation for complex high-dimensional state preparation and manipulation protocols in the frequency domain.

A protocol is presented for the practical generation and coherent manipulation of high-dimensional frequency-bin entangled photon states using integrated micro-cavities and standard telecommunications components, respectively.

We present a method for the generation and coherent manipulation of pulsed quantum frequency combs. Until now, methods of preparing high-dimensional ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...