This work was funded by the European Research Council (ERC) under the European Union&#8217;s Horizon 2020 research and innovation program (No.803004).

1. Preparation of the solution
<ol>
	<li>Prepare a solution containing prehydrolyzed tetraethyl orthosilicate (TEOS) 18 h before the production of the gel films in a fume hood in which a lab balance and a magnetic stirrer are placed.
	<ol>
		<li>Add 0.7 g of polyethylene glycol hexadecyl ether (Brij-58) and 23.26 g of ethanol into 50 mL bottle and close the lid of the bottle and stir it until the Brij is completely dissolved.</li>
		<li>Add 1.5 g of HCl 35% into the flask in step 1.1.1, close it and stir for 20 s.</li>
		<li>Add 4.22 g of TEOS to the flask in step 1.1.2, close it and let it stir for 18 h.</li>
	</ol>
	</li>
	<li>Preparation of 1 M aqueous solution of Sr2+ just before the production of the gel films because a matured solution is susceptible to re-precipitate in form of Sr salt.
	<ol>
		<li>Weigh 2.67 g of SrCl2&#183;6H2O in a 10 mL volumetric flask.</li>
		<li>Add 10 mL ultrapure water (e.g., Milli-Q) up to 10 mL into the flask in step 1.2.1 and close the flask with a plastic cap and gently shake the flask to dissolve the strontium chloride.</li>
	</ol>
	</li>
	<li>Add 275 &#181;L of the 1 M aqueous solution of Sr2+ into the 10 mL bottle containing the solution that was prepared in step 1.1 and stir the solution for 10 min.</li>
</ol>
2. Preparation of polydimethylsiloxane (PDMS) templates
<ol>
	<li>Preparation of PDMS solution after step 1.3.
	<ol>
		<li>Mix 1 part of the curing agent with 10 parts of the elastomer in a beaker on the balance. Stir the mixture with a glass stick until obtaining a homogeneous distribution of bubbles and remove it in a vacuum chamber.</li>
	</ol>
	</li>
	<li>Replicate the silicon master using the PDMS solution. Notice that for this work, we used a silicon patterned master composed of pillars with diameters, height, and separation distance of 1 &#181;m.
	<ol>
		<li>Put the silicon master with the structured face up in a plastic box and fill the box with the PDMS solution.</li>
		<li>Introduce the plastic box into the furnace at 70 &#176;C for 2 h to obtain a solid PDMS template.</li>
		<li>Separate the PDMS template and the silicon master. Cut the PDMS template to the desired size using a blade and keep it in a clean box.</li>
	</ol>
	</li>
</ol>
3. Gel film deposition on SOI (100) substrates by dip-coating
<ol>
	<li>Preparation of the substrates
	<ol>
		<li>Prepare 2 cm x 6 cm sized substrates by cutting a 2-inch p-type SOI wafer with the thickness of 2/0.5/0.67 &#181;m (Si/SiO2/Si) in a direction parallel or perpendicular to the wafer flat using a diamond tip. Notice that the conductivity of the silicon device layer must be between 1 and 10 &#8486;/cm.</li>
		<li>Introduce the substrates in a piranha solution for 20 min in order to eliminate possible&#160;polymer residues.</li>
		<li>Clean with DI water, then with ethanol, and let them dry or use nitrogen flow. This step should be performed just after step 1.3.</li>
	</ol>
	</li>
	<li>Deposition of a solution containing pre-hydrolyzed tetraethyl orthosilicate (TEOS), Brij-58 sulfactant and SrCl2 6H2O.
	<ol>
		<li>In order to obtain a homogeneous silica film, set the dip-coater&#8217;s chamber under the conditions at relative humidity 40% and 25 &#176;C of temperature.</li>
		<li>Place a beaker with the size of around 5 cm x 1 cm x 8 cm underneath the SOI substrate hanging from the dip-coater arm and establish a dip coating sequence with the speed of 300 mm/min at the immersion and withdrawal. Set the immersion time (time at the final position) to zero.</li>
		<li>Fill the beaker with the solution prepared in step 1.3 and wait until the relative humidity temperature becomes stable, i.e., 40% and 25 &#176;C, respectively.</li>
		<li>Perform a single dip coating and wait until the film becomes homogeneous.</li>
		<li>Introduce the SOI substrate into a furnace at 450 &#176;C for 5 min for the consilidation of the gel film to obtaine a thickness of 200 nm.</li>
		<li>Repeat steps 3.2.3 and 3.2.4 two times more to produce a film with around 600 nm of thickness. To ensure the stability of the solution, a repeating process should be performed in 1 h.</li>
	</ol>
	</li>
</ol>
4. Surface micro/nanostructuration by soft imprint lithography
<ol>
	<li>Prepare the micro/nano structures on the film surface under the conditions of relative humidity 40% and 25 &#176;C of temperature.
	<ol>
		<li>Repeat step 3.2.3 to deposit a new film on SOI substrate.</li>
		<li>Place the SOI substrate after step 3.2.1 on a flat surface and put the PDMS mold prepared in step 2.2 on the SOI substrate while the sol-gel is evaporating.</li>
		<li>Put the SOI substrate with the PDMS mold in a furnace at 70 &#176;C for 1 min, and then at 140 &#176;C for 2 min in a second furnace. Then, leave it for cooling down.</li>
		<li>Remove the PDMS mold to obtain a micro/nanostructured gel film on the SOI substrate.</li>
		<li>Introduce the SOI substrate into a furnace at 450 &#176;C for 5 min to consolidate a micro/nanostructured gel film with 600 nm height.</li>
	</ol>
	</li>
</ol>
5. Gel film crystallization by thermal treatment
<ol>
	<li>Thermal treatment of the gel films on SOI (100).
	<ol>
		<li>Program the tubular furnace heating from room temperature to 1000 &#176;C.</li>
		<li>Introduce the sample placed in a ceramic boat into the furnace at 1000 &#176;C for 5 hours. Do not cover the tubular working tube during the whole thermal treatment in order to saturate the furnace with air. Finally, reach the room temperature by cooling the furnace without any programmed ramp.</li>
	</ol>
	</li>
</ol>
6. Designing of lithography mask layout
The mask used in this process is designed specifically for a device fabrication on the SOI substrate with epitaxial nanostructured quartz. All the fabrication processes are carried out on the quartz side. The mask was designed in a way that negative tone resist needs to be used in each step. The mask is organized in four different steps as explained below.
<ol>
	<li>Pattern the quartz to determine the shape of the cantilever and also 30 &#181;m x 30 &#181;m square shape contact area. For example, 40 &#181;m x 100 &#181;m size rectangular shape cantilever area out of 120 &#181;m x 160 &#181;m area is protected with negative resist and the rest is etched until silicon layer.</li>
	<li>Realize the top and bottom electrodes. Top electrode is patterned on the rectangular shaped cantilever area and the bottom electrode is patterned on the 2 &#181;m thick silicon layer on the 30 &#181;m x 30 &#181;m etched area. The width of the top contact is 4 &#181;m smaller than the patterned cantilever area and the size of the bottom contact is bigger than the 30 &#181;m x 30 &#181;m square shape etched area in step 1.</li>
	<li>Etch all the 2 &#181;m thick silicon layers in 120 &#181;m x 160 &#181;m U-shaped area around the rectangle-shaped cantilever. The etched area is again U-shaped but 4 &#181;m smaller from each side to protect the cantilever area from HF attack in the last step.</li>
	<li>Release the cantilever with BOE etching of SiO2. The protected cantilever area is 2 &#181;m bigger than the actual cantilever area. The most important part is to protect the surface and blanks of the cantilever.</li>
</ol>
7. Cleaning of the quartz samples for the cantilever microfabrication process with piranha solution
<ol>
	<li>Prepare a piranha solution by slowly adding 10 mL of hydrogen peroxide (H2O2) into 20 mL of sulfuric acid (H2SO4) at ambient temperature. This mixture creates a thermal reaction.
	<ol>
		<li>Put the samples inside this solution for 10 min in order to clean all the organic residues.</li>
		<li>Rinse the samples with DI water and dry them with nitrogen.</li>
	</ol>
	</li>
</ol>
8. Step 1: Patterning cantilever shape on the quartz thin film
<ol>
	<li>The first lithography process
	<ol>
		<li>Rinse the samples with acetone, IPA, and then blow dry&#160;nitrogen.</li>
		<li>Put the samples on the hot plate at 140&#176;C for 10 min of dehumidification.</li>
		<li>Spin AZ2070 negative photoresist at a speed of 4000 rpm for 30 s.</li>
		<li>Put the samples on the hot plate to softbake at 115 &#176;C for 60 s.</li>
		<li>Expose the sample with 37.5 mJ.cm-2 UV dose for 5 s.</li>
		<li>Put the sample on the hot plate for post exposure bake at 115 &#176;C for 60 s.</li>
		<li>Develop in MIF 726 developer for 100 s at ambient temperature, then rinse in DI water and blow dry&#160;nitrogen. The expected thickness is 5.5 &#956;m.</li>
		<li>Put the sample on the hotplate at 125 &#176;C for 10 min to hardbake the resist.</li>
	</ol>
	</li>
	<li>Reactive Ion Etching (RIE) of the quartz layer
	<ol>
		<li>Etch the quartz until silicon layer using RIE with a gas flow rate of 60 sccm CHF3, 20 sccm 02, and 10 sccm Ar at 100 W RF power.</li>
	</ol>
	</li>
	<li>Cleaning the resist residuals
	<ol>
		<li>Clean with plasma at a flow rate of 90 sccm 02 for 5 min.</li>
		<li>If the first cleaning step is not enough, leave the sample in remover PG at 80 &#176;C until all the resists are removed.</li>
		<li>Then, put the sample in a piranha solution (20 mL of sulfuric acid H2SO4 + 10 mL of hydrogen peroxide H2O2) for 10 min. Then, rinse in DI water and blow dry with nitrogen.</li>
	</ol>
	</li>
</ol>
9. Step 2: Realization of bottom and top electrode
<ol>
	<li>The second lithography process
	<ol>
		<li>Rinse the samples with acetone, IPA, and then blow dry&#160;nitrogen.</li>
		<li>Put the samples on the hot plate at 140 &#176;C for 10 min of dehumidification.</li>
		<li>Spin AZ2020 negative photoresist at a speed of 4000 rpm for 30 s.</li>
		<li>Put the sample on the hot plate to softbake at 115 &#176;C for 60 s.</li>
		<li>Expose the sample with 23.25 mJ.cm-2 UV dose for 3 s.</li>
		<li>Put the sample on the hot plate for post exposure bake at 115 &#176;C for 60 s.</li>
		<li>Develop in MIF 726 developer for 50 s at ambient temperature, then rinse in DI water and blow dry&#160;nitrogen. The expected thickness is 1.7 &#956;m.</li>
	</ol>
	</li>
	<li>Metal deposition for top and bottom electrodes.
	<ol>
		<li>Deposit 50 nm Chromium at a rate of 4 A/s and 120 nm Platinum at 2.5 A/s with electron beam evaporation at 10-6 mbar.</li>
	</ol>
	</li>
	<li>Metal lift-off
	<ol>
		<li>Leave the samples firstly in acetone and then in IPA until metal lift off is successful.</li>
		<li>Check the sample with an optical microscope and if necessary, leave the sample in remover PG at 80 &#176;C until all metals lift-off. Then, rinse in DI water and blow dry&#160;nitrogen.</li>
		<li>If step 9.3.2 is not enough, put the samples in an ultrasonic cleaner in acetone for 5 min. Repeat this operation as many times as necessary.</li>
		<li>Rinse the samples with acetone, IPA, and then blow dry with nitrogen.</li>
	</ol>
	</li>
</ol>
10. Step 3: Patterning the sample to etch Si(100) layer
<ol>
	<li>The third lithography process
	<ol>
		<li>Rinse the samples with acetone, IPA, and then blow dry&#160;nitrogen.</li>
		<li>Put the samples on the hot plate at 140 &#176;C for 10 min of dehumidification.</li>
		<li>Spin AZ2070 negative photoresist at a speed of 2000 rpm for 30 s.</li>
		<li>Put the sample on the hotplate for softbake at 115 &#176;C for 60 s.</li>
		<li>Expose the sample with 37.5 mJ.cm-2 UV dose for 5 s.</li>
		<li>Put the sample on the hotplate for post exposure bake at 115 &#176;C for 60 s.</li>
		<li>Develop in MIF 726 for 110 s at ambient temperature, then rinse in DI water and blow dry with nitrogen. The expected thickness is 5.9 &#956;m.</li>
		<li>Put the sample on the hot plate at 125 &#176;C for 10 min to hardbake the resist.</li>
	</ol>
	</li>
	<li>Reactive Ion Etching of the silicon layer
	<ol>
		<li>Etch the silicon layer until SiO2 layer using RIE with gas flow rate of 60 sccm CHF3, 20 sccm 02 and 10 sccm Ar at 100W RF power.</li>
	</ol>
	</li>
	<li>Cleaning the resist residuals
	<ol>
		<li>First clean with plasma at a flow rate of 90 sccm 02 for 5 min.</li>
		<li>Leave the sample in remover PG at 80 &#176;C until all resists are removed. Then, rinse in DI water and blow dry&#160;nitrogen.</li>
	</ol>
	</li>
</ol>
11. Step 4: Releasing cantilever by wet chemical etching of SiO2
<ol>
	<li>The fourth lithography process
	<ol>
		<li>Rinse the samples with acetone, IPA, and then blow dry&#160;nitrogen.</li>
		<li>Put the samples on the hot plate at 140 &#176;C for 10 min of dehumidification.</li>
		<li>Spin AZ2020 negative photoresist at a speed of 2000 rpm for 30 s.</li>
		<li>Put the sample on the hotplate for soft bake at 115 &#176;C for 60 s.</li>
		<li>Expose the sample with 37.5 mJ.cm-2 UV dose for 5 s.</li>
		<li>Put the sample on the hotplate for post exposure bake at 115 &#176;C for 60 s.</li>
		<li>Develop in MIF 726 for 65 s at ambient temperature. Rinse in DI water and then blow dry&#160;nitrogen. The expected thickness is 2.3 &#956;m.</li>
		<li>Put the sample on the hotplate at 125 &#176;C for 10 min to hardbake the resist.</li>
	</ol>
	</li>
	<li>Wet etching of SiO2 layer with buffered oxide etch (BOE)
	<ol>
		<li>Put BOE 7:1 solution in a polytetrafluoroethylene (PTFE) based container.</li>
		<li>Put the sample in this solution and leave it at ambient temperature until all SiO2 layers are etched under the cantilever. Then rinse in DI water and blow dry nitrogen.</li>
	</ol>
	</li>
	<li>Cleaning the resist residuals
	<ol>
		<li>Rinse the samples with acetone, IPA, and then blow dry&#160;nitrogen.</li>
		<li>If necessary, clean the resist residuals with plasma at a flow rate of 90 sccm O2 for 5 min.</li>
	</ol>
	</li>
</ol>

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The authors have nothing to disclose.

The presented method is a combination of bottom-up and top-down approaches to produce nanostructured piezoelectric quartz micro-cantilevers on Si. Quartz/Si-MEMS technology offers major advantages over bulk quartz in terms of size, power consumption, and integration cost. Indeed, epitaxial quartz/Si MEMS are produced with CMOS-compatible processes. This could facilitate the future fabrication of single chip solutions for multifrequency devices while preserving miniaturization and cost-effective processes. Compared to the...

Oxide nanomaterials with piezoelectric properties are pivotal to design devices such as MEMS sensors or micro energy harvesters or storage1,2,3. As the advances in CMOS technology increase, the monolithic integration of high-quality epitaxial piezoelectric films and nanostructures into silicon becomes a subject of interest to expand new novel devices4. In addition, greater control of miniaturization of these devices is required to achieve high performances5,6. New sensor applications in electronic, biology, and medicine are enabled by the advances in micro and nanofabrication technologies7,8.
In particular, &#945;-quartz is widely used as a piezoelectric material and shows outstanding characteristics, which allow users to make fabrication for different applications. Although it has low electromechanical coupling factor, which limits its application area for energy harvesting, its chemical stability and high mechanical quality factor make it a good candidate for frequency control devices and sensor technologies9. However, these devices were micromachined from bulk single quartz crystals which have the desired characteristics for device fabrication10. The thickness of the quartz crystal should be configured in such a way that the highest resonance frequency can be obtained from the device, nowadays, the lowest achievable thickness is 10 &#956;m11. So far, some techniques to micropattern the bulk crystals such as Faraday cage angled-etching11, laser interference lithography12, and focused ion beam (FIB)13 were reported.
Recently, direct and bottom-up integration of epitaxial growth of (100) &#945;-quartz film into silicon substrate (100) was developed by chemical solution deposition (CSD)14,15. This approach opened a door to overcome the aforementioned challenges and also to develop piezoelectric-based devices for future sensor applications. Tailoring the structure of &#945;-quartz film on silicon substrate was achieved and it allowed to control the texture, density, and the thickness of the film16. The thickness of the &#945;-quartz film was extended from a few hundred nanometers to the micron range, which are 10 to 50 times thinner than those obtained by top-down technologies on bulk crystal. Optimizing the dip-coating deposition conditions, humidity and temperature was enabled to attain both continuous nanostructured crystalline quartz film and a perfect nanoimprinted pattern by a combination of a set of top-down lithography techniques17. Specifically, soft nanoimprint lithography (NIL) is a low-cost, large-scale fabrication and benchtop equipment-based process. Application of soft NIL, which combines top-down and bottom-up approaches, is a key to produce epitaxial quartz nanopillar arrays on silicon with a precise control of pillar diameters, height, and the interpillar distances. Furthermore, fabrication of silica nanopillar with controlled shape, diameter, and periodicity on borosilicate glass for a biological application was performed customizing soft NIL of epitaxial quartz thin film18.
Up to now, it has not been possible for on-chip integration of piezoelectric nanostructured &#945;-quartz MEMS. Here, we draw the detailed engineering route starting from material to device fabrication. We explain all the steps for material synthesis, soft NIL, and the microfabrication of the device to release a piezoelectric quartz cantilever on SOI substrate19 and discuss its response as a piezoelectric material with some characterization results.

<table><tbody><tr><td>Acetone</td><td>Honeywell Riedel de Ha&amp;euml;n</td><td>UN 1090</td><td></td></tr><tr><td>AZnLOF 2020 negative resist</td><td>Microchemicals</td><td>USAW176488-1BLO</td><td></td></tr><tr><td>AZnLOF 2070 negative resist</td><td>Microchemicals</td><td>USAW211327-1FK6</td><td></td></tr><tr><td>AZ 726 MIF developer</td><td>Merck</td><td>DEAA195539</td><td></td></tr><tr><td>BOE (7:1)</td><td>Technic</td><td>AF 87.5-12.5</td><td></td></tr><tr><td>Brij-58</td><td>Sigma</td><td>9004-95-9</td><td></td></tr><tr><td>Chromium</td><td>Neyco</td><td>FCRID1T00004N-F53-062317/FC79271</td><td></td></tr><tr><td>Dip Coater ND-R 11/2 F</td><td>Nadetec</td><td>ND-R 11/2 F</td><td></td></tr><tr><td>Hydrogen peroxide solution 30%</td><td>Carlo Erka Reagents DasitGroup</td><td>UN 2014</td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt;SO&lt;sub&gt;4&lt;/sub&gt;</td><td>Honeywell Fluka</td><td>UN 1830</td><td></td></tr><tr><td>Isopropyl alcohol</td><td>Honeywell Riedel de Ha&amp;euml;n</td><td>UN 1219</td><td></td></tr><tr><td>Mask aligner</td><td>EV Group</td><td>EVG620</td><td></td></tr><tr><td>PG remover</td><td>MicroChem</td><td>18111026</td><td></td></tr><tr><td>Platinum</td><td>Neyco</td><td>INO272308/F14508</td><td></td></tr><tr><td>PTFE based container</td><td>Teflon</td><td></td><td></td></tr><tr><td>Reactive ion etching (RIE)</td><td>Corial</td><td>ICP Corial 200 IL</td><td></td></tr><tr><td>SEMFEG</td><td>Hitachi</td><td>Su-70</td><td></td></tr><tr><td>SOI substrate</td><td>University Wafer</td><td>ID :3213</td><td></td></tr><tr><td>Strontium chloride hexahydrate</td><td>Sigma-Aldrich</td><td>10025-70-4</td><td></td></tr><tr><td>SYLGARD TM 184 Silicone Elastomer Kit</td><td>Dow</td><td>.000000840559</td><td></td></tr><tr><td>SYLGARD TM 184 Silicone Elastomer Curring Agent</td><td>Dow</td><td>.000000840559</td><td></td></tr><tr><td>Tetraethyl orthosilicate</td><td>Aldrich</td><td>78-10-4</td><td></td></tr><tr><td>Tubular Furnace</td><td>Carbolite</td><td>PTF 14/75/450</td><td></td></tr><tr><td>Vibrometer</td><td>Polytec</td><td>OFV-500D</td><td></td></tr><tr><td>2D XRD</td><td>Bruker</td><td>D8 Discover</td><td>Equipped with a Eiger2 R 500 K 2D detector</td></tr></tbody></table>

epitaxial nanostructured &alpha;-quartz films on silicon: from the material to new devices

In this work, we show a detailed engineering route of the first piezoelectric nanostructured epitaxial quartz-based microcantilever. We will explain all the steps in the process starting from the material to the device fabrication. The epitaxial growth of &#945;-quartz film on SOI (100) substrate starts with the preparation of a strontium doped silica sol-gel and continues with the deposition of this gel into the SOI substrate in a thin film form using the dip-coating technique under atmospheric conditions at room temperature. Before crystallization of the gel film, nanostructuration is performed onto the film surface by nanoimprint lithography (NIL). Epitaxial film growth is reached at 1000 &#176;C, inducing a perfect crystallization of the patterned gel film. Fabrication of quartz crystal cantilever devices is a four-step process based on microfabrication techniques. The process starts with shaping the quartz surface, and then metal deposition for electrodes follows it. After removing the silicone, the cantilever is released from SOI substrate eliminating SiO2 between silicon and quartz. The device performance is analyzed by non-contact laser vibrometer (LDV) and atomic force microscopy (AFM). Among the different cantilever&#8217;s dimensions included in the fabricated chip, the nanostructured cantilever analyzed in this work exhibited a dimension of 40 &#181;m large and 100 &#181;m long and was fabricated with a 600 nm thick patterned quartz layer (nanopillar diameter and separation distance of 400 nm and 1 &#181;m, respectively) epitaxially grown on a 2 &#181;m thick Si device layer. The&#160;measured&#160;resonance frequency was&#160;267 kHz and the estimated quality factor, Q, of the whole mechanical structure was Q ~ 398 under low vacuum conditions. We observed the voltage-dependent linear displacement of cantilever with both techniques (i.e., AFM contact measurement and LDV). Therefore, proving that these devices can be activated through the indirect piezoelectric effect.

The progress of the material synthesis and device fabrication (see Figure 1) was depicted schematically by monitoring different steps with real images. After the microfabrication processes, we observed the aspect of the nanostructured cantilevers using the field emission Scanning Electron Microscopy (FEG-SEM) images (Figure 2a-c). 2D Micro X-ray diffraction controlled the crystallinity of the different stacking layers of the cantilever (<strong ...

Watch this Scientific Journal Video about Epitaxial Nanostructured Î±-Quartz Films on Silicon: From the Material to New Devices at JoVE.com

Epitaxial Nanostructured &#945;-Quartz Films on Silicon: From the Material to New Devices

This work presents a detailed protocol for the microfabrication of nanostructured &#945;-quartz cantilever on a Silicon-On-Insulator(SOI) technology substrate starting from the epitaxial growth of quartz film with the dip coating method and then nanostructuration of the thin film via nanoimprint lithography.

Epitaxial Nanostructured &alpha;-Quartz Films on Silicon: From the Material to New Devices

In this work, we show a detailed engineering route of the first piezoelectric nanostructured epitaxial quartz-based microcantilever. We will explain all ...

epitaxial-nanostructured-quartz-films-on-silicon-from-material-to-new

Research

JoVE Journal

Engineering

5.4K Views.  Université de Montpellier. Dit werk presenteert een gedetailleerd protocol voor de microfabrication van nanogestructureerde α-kwarts cantilever op een Silicon-On-Insulator (SOI) technologiesubstraat beginnend bij de epitaxiale groei van kwartsfilm met de dipcoatingmethode en vervolgens nanostructuratie van de dunne film via nanoimprintlithografie.

Video: Epitaxial Nanostructured α-Quartz Films on Silicon: From the Material to New Devices

Harvesting Solar Energy by Means of Charge-Separating Nanocrystals and Their Solids

Conjoining different semiconductor materials in a single nano-composite provides synthetic means for the development of novel optoelectronic materials offering a superior control over the spatial distribution of charge carriers across material interfaces. As this study demonstrates, a combination of donor-acceptor nanocrystal (NC) domains in a single nanoparticle can lead to the realization of efficient photocatalytic1-5 materials, while a layered assembly of donor- and acceptor-like nanocrystals films gives rise to photovoltaic materials.
Initially the paper focuses on the synthesis of composite inorganic nanocrystals, comprising linearly stacked ZnSe, CdS, and Pt domains, which jointly promote photoinduced charge separation. These structures are used in aqueous solutions for the photocatalysis of water under solar radiation, resulting in the production of H2 gas. To enhance the photoinduced separation of charges, a nanorod morphology with a linear gradient originating from an intrinsic electric field is used5. The inter-domain energetics are then optimized to drive photogenerated electrons toward the Pt catalytic site while expelling the holes to the surface of ZnSe domains for sacrificial regeneration (via methanol). Here we show that the only efficient way to produce hydrogen is to use electron-donating ligands to passivate the surface states by tuning the energy level alignment at the semiconductor-ligand interface. Stable and efficient reduction of water is allowed by these ligands due to the fact that they fill vacancies in the valence band of the semiconductor domain, preventing energetic holes from degrading it. Specifically, we show that the energy of the hole is transferred to the ligand moiety, leaving the semiconductor domain functional. This enables us to return the entire nanocrystal-ligand system to a functional state, when the ligands are degraded, by simply adding fresh ligands to the system4.
To promote a photovoltaic charge separation, we use a composite two-layer solid of PbS and TiO2 films. In this configuration, photoinduced electrons are injected into TiO2 and are subsequently picked up by an FTO electrode, while holes are channeled to a Au electrode via PbS layer6. To develop the latter we introduce a Semiconductor Matrix Encapsulated Nanocrystal Arrays (SMENA) strategy, which allows bonding PbS NCs into the surrounding matrix of CdS semiconductor. As a result, fabricated solids exhibit excellent thermal stability, attributed to the heteroepitaxial structure of nanocrystal-matrix interfaces, and show compelling light-harvesting performance in prototype solar cells7.

A general strategy for the development of charge-separating semiconductor nanocrystal composites deployable for solar energy production is presented. We show that assembly of donor-acceptor nanocrystal domains in a single nanoparticle geometry gives rise to a photocatalytic function, while bulk-heterojunctions of donor-acceptor nanocrystal films can be used for photovoltaic energy conversion.

Conjoining different semiconductor materials in a single nano-composite provides synthetic means for the development of novel optoelectronic materials ...

Atomically Defined Templates for Epitaxial Growth of Complex Oxide Thin Films

Atomically defined substrate surfaces are prerequisite for the epitaxial growth of complex oxide thin films. In this protocol, two approaches to obtain such surfaces are described. The first approach is the preparation of single terminated perovskite SrTiO3 (001) and DyScO3 (110) substrates. Wet etching was used to selectively remove one of the two possible surface terminations, while an annealing step was used to increase the smoothness of the surface. The resulting single terminated surfaces allow for the heteroepitaxial growth of perovskite oxide thin films with high crystalline quality and well-defined interfaces between substrate and film. In the second approach, seed layers for epitaxial film growth on arbitrary substrates were created by Langmuir-Blodgett (LB) deposition of nanosheets. As model system Ca2Nb3O10- nanosheets were used, prepared by delamination of their layered parent compound HCa2Nb3O10. A key advantage of creating seed layers with nanosheets is that relatively expensive and size-limited single crystalline substrates can be replaced by virtually any substrate material.

Various procedures are outlined to prepare atomically defined templates for epitaxial growth of complex oxide thin films. Chemical treatments of single crystalline SrTiO3 (001) and DyScO3 (110) substrates were performed to obtain atomically smooth, single terminated surfaces. Ca2 Nb3 O10- nanosheets were used to create atomically defined templates on arbitrary substrates.

Atomically defined substrate surfaces are prerequisite for the epitaxial growth of complex oxide thin films. In this protocol, two approaches to obtain ...

Chemistry

Selective Area Modification of Silicon Surface Wettability by Pulsed UV Laser Irradiation in Liquid Environment

The wettability of silicon (Si) is one of the important parameters in the technology of surface functionalization of this material and fabrication of biosensing devices. We report on a protocol of using KrF and ArF lasers irradiating Si (001) samples immersed in a liquid environment with low number of pulses and operating at moderately low pulse fluences to induce Si wettability modification. Wafers immersed for up to 4 hr in a 0.01% H2O2/H2O solution did not show measurable change in their initial contact angle (CA) ~75&#176;. However, the 500-pulse KrF and ArF lasers irradiation of such wafers in a microchamber filled with 0.01% H2O2/H2O solution at 250 and 65 mJ/cm2, respectively, has decreased the CA to near 15&#176;, indicating the formation of a superhydrophilic surface. The formation of OH-terminated Si (001), with no measurable change of the wafer&#8217;s surface morphology, has been confirmed by X-ray photoelectron spectroscopy and atomic force microscopy measurements. The selective area irradiated samples were then immersed in a biotin-conjugated fluorescein-stained nanospheres solution for 2 hr, resulting in a successful immobilization of the nanospheres in the non-irradiated area. This illustrates the potential of&#160;the method for selective area biofunctionalization and fabrication of advanced Si-based biosensing architectures. We also describe a similar protocol of irradiation of wafers immersed in methanol (CH3OH) using ArF laser operating at pulse fluence of 65 mJ/cm2 and in situ formation of a strongly hydrophobic surface of Si (001) with the CA of 103&#176;. The XPS results indicate ArF laser induced formation of Si&#8211;(OCH3)x compounds responsible for the observed hydrophobicity. However, no such compounds were found by XPS on the Si surface irradiated by KrF laser in methanol, demonstrating the inability of the KrF laser to photodissociate methanol and create -OCH3 radicals.

We report on a process of in situ alteration of HF treated Si (001) surface into a hydrophilic or hydrophobic state by irradiating samples in microfluidic chambers filled with&#160;H2O2/H2O solution (0.01%-0.5%) or methanol solutions using pulsed UV laser of a relative low pulse fluence.

The wettability of silicon (Si) is one of the important parameters in the technology of surface functionalization of this material and fabrication of ...

Fabrication and Operation of a Nano-Optical Conveyor Belt

The technique of using focused laser beams to trap and exert forces on small particles has enabled many pivotal discoveries in the nanoscale biological and physical sciences over the past few decades. The progress made in this field invites further study of even smaller systems and at a larger scale, with tools that could be distributed more easily and made more widely available. Unfortunately, the fundamental laws of diffraction limit the minimum size of the focal spot of a laser beam, which makes particles smaller than a half-wavelength in diameter hard to trap and generally prevents an operator from discriminating between particles which are closer together than one half-wavelength. This precludes the optical manipulation of many closely-spaced nanoparticles and&#160;limits the&#160;resolution of optical-mechanical systems. Furthermore, manipulation using focused beams requires beam-forming or steering optics, which can be very bulky and expensive. To address these limitations in the system scalability of conventional optical trapping our lab has devised an alternative technique which utilizes near-field optics to move particles across a chip. Instead of focusing laser beams in the far-field, the optical near field of plasmonic resonators produces the necessary local optical intensity enhancement to overcome the restrictions of diffraction and manipulate particles at higher resolution. Closely-spaced resonators produce strong optical traps which can be addressed to mediate the hand-off of particles from one to the next in a conveyor-belt-like fashion. Here, we describe how to design and produce a conveyor belt using a gold surface patterned with plasmonic C-shaped resonators and how to operate it with polarized laser light to achieve super-resolution nanoparticle manipulation and transport. The nano-optical conveyor belt chip can be produced using lithography techniques and easily packaged and distributed.

The scalability and resolution of conventional optical manipulation techniques are limited by diffraction. We circumvent the diffraction limit and describe a method of optically transporting nanoparticles across a chip using a gold surface patterned with a path of closely spaced C-shaped plasmonic resonators.

The technique of using focused laser beams to trap and exert forces on small particles has enabled many pivotal discoveries in the nanoscale biological ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

Atomically Traceable Nanostructure Fabrication

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process being used in order to maintain exquisite control over both feature size and feature density. Here, we demonstrate a method for tracking atomically resolved and controlled structures from initial template definition through final nanostructure metrology, opening up a pathway for top-down atomic control over nanofabrication. Hydrogen depassivation lithography is the first step of the nanoscale fabrication process followed by selective atomic layer deposition of up to 2.8 nm of titania to make a nanoscale etch mask. Contrast with the background is shown, indicating different mechanisms for growth on the desired patterns and on the H passivated background. The patterns are then transferred into the bulk using reactive ion etching to form 20 nm tall nanostructures with linewidths down to ~6 nm. To illustrate the limitations of this process, arrays of holes and lines are fabricated. The various nanofabrication process steps are performed at disparate locations, so process integration is discussed. Related issues are discussed including using fiducial marks for finding nanostructures on a macroscopic sample and protecting the chemically reactive patterned Si(100)-H surface against degradation due to atmospheric exposure.

We report a protocol for combining the atomic metrology of the Scanning Tunneling Microscope for surface patterning with selective Atomic Layer Deposition and Reactive Ion Etching. Using a robust process involving numerous atmospheric exposures and transport, 3D nanostructures with atomic metrology are fabricated.

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process ...

Preparation of Macroporous Epitaxial Quartz Films on Silicon by Chemical Solution Deposition

This work describes the detailed protocol for preparing piezoelectric macroporous epitaxial quartz films on silicon(100) substrates. This is a three-step process based on the preparation of a sol in a one-pot synthesis which is followed by the deposition of a gel film on Si(100) substrates by evaporation induced self-assembly using the dip-coating technique and ends with a thermal treatment of the material to induce the gel crystallization and the growth of the quartz film. The formation of a silica gel is based on the reaction of a tetraethyl orthosilicate and water, catalyzed by HCl, in ethanol. However, the solution contains two additional components that are essential for preparing mesoporous epitaxial quartz films from these silica gels dip-coated on Si. Alkaline earth ions, like Sr2+ act as glass melting agents that facilitate the crystallization of silica and in combination with cetyl trimethylammonium bromide (CTAB) amphiphilic template form a phase separation responsible of the macroporosity of the films. The good matching between the quartz and silicon cell parameters is also essential in the stabilization of quartz over other SiO2 polymorphs and is at the origin of the epitaxial growth.

A protocol is presented for the preparation of piezoelectric macroporous epitaxial films of quartz on silicon by solution chemistry using dip-coating and thermal treatments in air.

This work describes the detailed protocol for preparing piezoelectric macroporous epitaxial quartz films on silicon(100) substrates. This is a three-step ...

Epitaxial Growth of Perovskite Strontium Titanate on Germanium via Atomic Layer Deposition

Atomic layer deposition (ALD) is a commercially utilized deposition method for electronic materials. ALD growth of thin films offers thickness control and conformality by taking advantage of self-limiting reactions between vapor-phase precursors and the growing film. Perovskite oxides present potential for next-generation electronic materials, but to-date have mostly been deposited by physical methods. This work outlines a method for depositing SrTiO3 (STO) on germanium using ALD. Germanium has higher carrier mobilities than silicon and therefore offers an alternative semiconductor material with faster device operation. This method takes advantage of the instability of germanium's native oxide by using thermal deoxidation to clean and reconstruct the Ge (001) surface to the 2&#215;1 structure. 2-nm thick, amorphous STO is then deposited by ALD. The STO film is annealed under ultra-high vacuum and crystallizes on the reconstructed Ge surface. Reflection high-energy electron diffraction (RHEED) is used during this annealing step to monitor the STO crystallization. The thin, crystalline layer of STO acts as a template for subsequent growth of STO that is crystalline as-grown, as confirmed by RHEED. In situ X-ray photoelectron spectroscopy is used to verify film stoichiometry before and after the annealing step, as well as after subsequent STO growth. This procedure provides framework for additional perovskite oxides to be deposited on semiconductors via chemical methods in addition to the integration of more sophisticated heterostructures already achievable by physical methods.

This work details the procedures for the growth and characterization of crystalline SrTiO3 directly on germanium substrates by atomic layer deposition. The procedure illustrates the ability of an all-chemical growth method to integrate oxides monolithically onto semiconductors for metal-oxide semiconductor devices.

Atomic layer deposition (ALD) is a commercially utilized deposition method for electronic materials. ALD growth of thin films offers thickness control and ...

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and forging. Adoption of this technique is proceeding despite disagreement concerning the underlying mechanism responsible for EAD. The experimental procedure described herein enables a more explicit study compared to previous EAD research by removing thermal effects, which are responsible for disagreement in interpreting previous EAD results. Furthermore, as the procedure described here enables EAD observation in situ and in real time in a transmission electron microscope (TEM), it is superior to existing post-mortem methods that observe EAD effects post-test. Test samples consist of a single crystal copper (SCC) foil having a free-standing tensile test section of nanoscale thickness, fabricated using a combination of laser and ion beam milling. The SCC is mounted to an etched silicon base that provides mechanical support and electrical isolation while serving as a heat sink. Using this geometry, even at high current density (~3,500 A/mm2), the test section experiences a negligible temperature increase (&#60;0.02 &#176;C), thus eliminating Joule heating effects. Monitoring material deformation and identifying the corresponding changes to microstructures, e.g. dislocations, are accomplished by acquiring and analyzing a series of TEM images. Our sample preparation and in situ experiment procedures are robust and versatile as they can be readily utilized to test materials with different microstructures, e.g., single and polycrystalline copper.

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Isolating electrical and thermal effects on electrically assisted deformation (EAD) is very difficult using macroscopic samples. Metallic sample micro- and nanostructures together with a custom test procedure have been developed to evaluate the impact of applied current on the formation without joule heating and evolution of dislocations on these samples.

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and ...

Graphene-Assisted Quasi-van der Waals Epitaxy of AlN Film on Nano-Patterned Sapphire Substrate for Ultraviolet Light Emitting Diodes

This protocol demonstrates a method for graphene-assisted quick growth and coalescence of AlN on nano-pattened sapphire substrate (NPSS). Graphene layers are directly grown on NPSS using catalyst-free atmospheric-pressure chemical vapor deposition (APCVD). By applying nitrogen reactive ion etching (RIE) plasma treatment, defects are introduced into the graphene film to enhance chemical reactivity. During metal-organic chemical vapor deposition (MOCVD) growth of AlN, this N-plasma treated graphene buffer enables AlN quick growth, and coalescence on NPSS is confirmed by cross-sectional scanning electron microscopy (SEM). The high quality of AlN on graphene-NPSS is then evaluated by X-ray rocking curves (XRCs) with narrow (0002) and (10-12) full width at half-maximum (FWHM) as 267.2 arcsec and 503.4 arcsec, respectively. Compared to bare NPSS, AlN growth on graphene-NPSS shows significant reduction of residual stress from 0.87 GPa to 0.25 Gpa, based on Raman measurements. Followed by AlGaN multiple quantum wells (MQWS) growth on graphene-NPSS, AlGaN-based deep ultraviolet light-emitting-diodes (DUV LEDs) are fabricated. The fabricated DUV-LEDs also demonstrate obvious, enhanced luminescence performance. This work provides a new solution for the growth of high quality AlN and fabrication of high performance DUV-LEDs using a shorter process and less costs.

A protocol for graphene-assisted growth of high-quality AlN films on nano-patterned sapphire substrate is presented.

This protocol demonstrates a method for graphene-assisted quick growth and coalescence of AlN on nano-pattened sapphire substrate (NPSS). Graphene layers ...

Epitaxial Nanostructured α-Quartz Films on Silicon: From the Material to New Devices

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