In this protocol, we are showing the fabrication process of cross-point devices incorporating amorphous vanadium oxide, which actually dissolves in the water.And further, this protocol helps us to improve our understanding of nano-structural changes during the biasing operations.This protocol allows a visual analysis of nano-structural changes related to device biasing, and can be extended to any metal-insulator-metal device structure that's compatible with high vacuum.This protocol can be easily extended to do in-situ temperature or temperature and biasing together analysis to reveal the atomic level changes happening within the device.To pattern the bottom of the electrode of the cross-point device with photoresist, first spin coat the photoresist onto the wafer at 3000 revolutions per minute, before soft baking at 95 degrees Celsius for 60 seconds.Next, use a 405 nanometer laser to expose the device to 25 millijoules per square centimeter, and bake at 120 degrees Celsius for 120 seconds.Use a 400 nanometer laser to flood-expose the device with 21 milliwatts per square centimeter, and use developer to develop the pattern.Rinse the device with de-ionized water, and use a physical vapor deposition system to deposit 10 nanometers of titanium and 100 nanometers of platinum onto the substrate pattern on layer one.To lift off the deposited metals, place the substrate in an acetone bath for approximately 20 minutes before applying ultrasonic vibrations for two minutes and rinsing with acetone and isopropyl alcohol.Repeat the process until the clean-patterned wafers are achieved.Repeat the same photolithography, or patterning process, to pattern the second layer of amorphous vanadium oxide and the third layer onto the top of the electrode with 20 nanometer titanium and 200 nanometer platinum.For mounting of the biasing chip, first clean the chip in a glass Petri dish filled with acetone with gentle rotation for two minutes.After washing, transfer the chip into a Petri dish filled with methanol for an additional two minutes of rotation before blowing the chip dry with low-pressured nitrogen.Align the dried-biasing chip in square trenches of gridbar, and use screws to fix the grid cover onto the biasing chip, finalizing the placement of the e-chip on the gridbar.To mount the biasing chip with lamella, use conductive carbon tape to mount the newly-prepared sample onto a metal stub, and load the stub into a Focused Ion Beam chamber.Apply additional tape on the sample for grounding to avoid charging issues, and load the biasing chip-mounted gridbar in the chamber at a 52 degree angle.Use the microscope physical control panel and software to focus, as and align the electron beam on a sample surface, and check the eucentric height of the focused sample location and beam coincidence for the electron and ion beams.Click the AutoTem program to run the program on the focused sample location, and use silicone milling to create cross-fiducial alignment markers.Deposit a 1.5 micrometer thick carbon protective layer over the 20/5 micrometer area between the alignment markers, and use a 5 nanoangstrom beam current to mill trenches on either side of the carbon protective layer.Thin the lamella with subsequent 1 nanoangstrom and a 300 picoangstrom ion beam currents to reach a 1 micrometer thickness.Tilt the sample to seven degrees to perform a J-cut on the lamella for separation from the substrate.To attach the lamella to the manipulator needle, tilt the sample to zero degrees and use platinum to attach the lamella to the needle.After attaching to the micro manipulator, use a final cut to separate the lamella from the substrate and slowly retract the micro manipulator.Focus the beam on the top edge of the biasing chip on the gridbar, and use the needle to bring the lamella slowly toward the biasing chip.Align the lamella in the center of the 17 micrometer gap on the top edge of the biasing chip, and slowly move the gap down until it barely touches the chip surface.Use platinum to weld the bottom edges of the lamella to the chip, and use Silicon milling to cut the micro manipulator free from the lamella.Retract the micro manipulator, and connect the top edges of the lamella with platinum traces to the two electrodes of the biasing chip.Tilting the specimen front and back by two degrees to ensure parallel faces and a uniform thickness.Use a consecutive 300 picoangstrom and 100 picoangstrom beam to thin the center region of the lamella to less than 100 nanometers thick.Polish out the ion beam-damaged layer with the gallium-beam accelerating voltage of five kilovolts at a five degree angle to the surface on both faces, and use isolation cuts in the thinned region to remove the short connection between the top and bottom electrodes of the device to create a current path from the bottom to the top electrode through the active region.Then, mount the biasing chip with the lamella on the biasing chip holder, and load the biasing chip holder into the Transmission Electron Microscopy chamber.For in-situ Transmission Electron Microscopy Imaging, carefully connect the wires from the biasing chip holder to the source meter and a control computer.When the Transmission Electron Microscopy chamber pressure drops to the desired value, use the Transmission Electron Microscopy control knobs to focus and align the electron beam on a cross-section of the lamella surface, and apply voltage sweeps, collecting the Transmission Electron Microscopy micrographs in-situ.In-situ nano-structural changes occurring within the lamella on the application of bias can then be observed.In this image, a representative Transmission Electron Microscopy micrograph of the intact lamella can be observed.The diffraction patterns in the inset indicate the amorphous nature of the oxide film.At four volts, a localized crystalline region forms in the oxide layer.In this analysis, d-spacing was 0.35 nanometers, corresponding to the 011 plane of the vanadium oxide M1 phase.At five volts, multiple localized crystal islands oriented in different directions with respect to the substrate can be observed within the oxide.A d-spacing of 0.27 nanometers corresponding to the vanadium oxide A phase and a d-spacing of 0.26 nanometers corresponding to the vanadium oxide M1 phase are apparent.At six volts, moir
