Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Podsumowanie

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Streszczenie

We demonstrate a method for the low temperature growth (350 °C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

Wprowadzenie

Copper and tungsten, the metals which are currently used for the interconnects in state-of-the-art very-large-scale integration (VLSI) technology, are approaching their physical limits in terms of reliability and electrical conductivity¹. While down-scaling transistors generally improves their performance, it actually increases the resistance and current density of the interconnects. This resulted in interconnects dominating the integrated circuit (IC) performance in terms of delay and power consumption².

Carbon nanotubes (CNT) have been suggested as alternative for Cu and W metallization, especially for vertical interconnects (vias) as CNT can easily been grown vertical³. CNT have been shown to have excellent electrical reliability, allowing an up to 1,000 times higher current density than Cu⁴. Moreover, CNT do not suffer from surface and grain boundary scattering, which is increasing the resistivity of Cu at the nanometer scale⁵. Finally, CNT have been shown to be excellent thermal conductors⁶, which can aid in the thermal management in VLSI chips.

For successful integration of CNT in VLSI technology it is important that the growth processes for the CNT is made compatible with semiconductor fabrication. This requires the low temperature growth of CNT (< 400 °C) using materials and equipment which are considered compatible and scalable to large scale manufacturing. While many examples of CNT test vias have been demonstrated in the literature^{7,8,9,10,11,12,13,14}, most of these use Fe as catalyst which is regarded as a contaminant in IC manufacturing¹⁵. Besides, the growth temperature used in many of these works is much higher than the upper limit of 400 °C. Preferably CNT should even be grown below 350 °C, in order to allow integration with modern low-κ dielectrics or flexible substrates.

Here we present a scalable method for growing CNT at temperatures as low as 350 °C using Co as catalyst¹⁶. This method is of interest for fabricating different electrical structures consisting of vertically aligned CNT in integrated circuits, ranging from interconnect and electrodes to super capacitors and field emission devices. The Co catalyst metal is often used in IC manufacturing for the fabrication of silicide’s¹⁷, while TiN is an often used barrier material⁷. Moreover, we demonstrate a process for fabricating CNT test vias while only using techniques from standard semiconductor manufacturing. With this, CNT test vias are fabricated, inspected by scanning electron microscopy (SEM) and Raman spectroscopy, and electrically characterized.

Protokół

Caution: Please consult all relevant material safety data sheets (MSDS) before use. Several of the chemicals used in this fabrication process are acutely toxic and carcinogenic. Nanomaterials may have additional hazards compared to their bulk counterpart. Please use all appropriate safety practices when working with equipment, chemicals or nanomaterials, including the use of engineering controls (fume hood) and personal protective equipment (safety glasses, gloves, cleanroom clothes).

1. Alignment Marker Definition for Lithography

1. Start with single-sided polished industrial grade Si(100) wafers with either n or p-type doping.
2. Coat the wafer with 1.4 µm of positive photoresist. Perform a 90 sec hexamethyldisilazane (HMDS) treatment at 130 °C to promote adhesion of the photoresist, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 °C.
3. Using a photo-lithography mask and exposure tool expose the alignment markers, exposure dose 120 mJ/cm²_.
4. Perform a single puddle development process. Perform a 90 sec 115 °C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 °C to cure the resist.
5. Use a microscope to inspect if the openings in the resist are of the correct dimensions.
6. Etch 120 nm of Si using chlorine plasma etching. This thickness gives good contrast for the automatic alignment systems of the exposure tool used in this work. For example using an inductive coupled plasma (ICP): 20/40 sccm O₂/CF₄, 5 mTorr, 60/500 W platen/ICP RF power, 10 sec oxide breakthrough etching, followed by 80/40 sccm Cl₂/HBr, 60 mTorr, 20/500 W platen/ICP RF power, 35 sec Si etch.
7. Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O₂ with endpoint detection and 2 min overetch). As the photoresist is cured by the plasma normal solvent like acetone cannot be used.
8. Clean the wafers. First put them for 10 min in 99% HNO₃, followed by rinsing in DI water till the resistivity of the water is 5 MΩ (organic clean). After this clean the wafers for 10 min in 65% HNO₃ at 110 °C, followed by rinsing with DI water till the resistivity of the water is 5 MΩ (metal clean). Use a rinser dryer to dry the wafers.

2. Bottom Metal and Interlayer Dielectric Deposition

1. Use magnetron sputtering to deposit the bottom metal layer of the test via. A stack of three metal layers needs to be deposited: 500 nm of Ti, 50 nm of TiN, and 100 nm Ti. The first Ti layer is to reduce the resistance of the stack, the TiN is the actual support layer for CNT growth, and the top Ti is to protect the TiN against plasma damage when etching the SiO₂ layer¹². Perform Ti sputtering using a pure Ti target with Ar-plasma at a substrate temperature of 350 °C. For TiN reactive sputtering use a combination of Ar and N₂, again at 350 °C substrate temperature.
2. Using plasma-enhanced chemical vapor deposition (PECVD), deposit a 1 µm thick layer of SiO₂. Here tetraethyl orthosilicate (TEOS) is used as precursor at a platen temperature of 350 °C.
   1. Check the thickness of the SiO₂ layer using an appropriate tool, for instance a reflectometer or ellipsometer.
3. Coat the wafer with 1.4 µm of positive photoresist, starting with a 90 sec HMDS treatment at 130 °C, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 °C.
4. Using a photo-lithography mask and exposure tool, expose the desired pattern of openings, which will be later etched into the SiO₂ to form the vias, aligned to the alignment markers, exposure dose 140 mJ/cm²_.
5. Perform a single puddle development process starting with a 90 sec 115 °C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 °C.
6. Use a microscope to inspect if the openings in the resist are of the correct dimensions and if the overlay to the alignment markers is correct.
7. Plasma etch the contact openings in the SiO₂. For example, use a triode plasma etcher with C₂F₆/CHF₃ 36/144 sccm at 180 mTorr and 300 W RF power. If necessary, perform etch rate tests on a test wafer in order to minimize over etching to 5%-10% in time.
   Note: Although the Ti is resistant to reactive etching in this fluorine chemistry, prolonged exposure to the plasma will result in physical etching of the Ti layer. If the TiN layer is exposed to the plasma this will have a negative influence on the growth of the CNT¹². Do not use wet etching as this will result in too much widening of the openings, making the top metallization in part 4 problematic.
8. Remove the sacrificial Ti layer by wet etching in 0.55% HF for 60 sec. After etching rinse the wafers with DI water till the water resistivity is 5 MΩ and use a rinser dryer to dry the wafers.
   Note: Using a microscope it can be checked if the Ti layer is etched, the TiN layer will have a gold-brown color while the Ti is metallic grey.

3. Catalyst Deposition and CNT Growth

1. Evaporate 5 nm of Co using an e-beam evaporator. Pump down till at least 2x10^-6 Torr, and heat the wafers to 60 °C using lamps under vacuum before depositing to remove any water film. The photo-resist used to define the contact openings is kept on the wafer to provide self-alignment of the catalyst to the contact openings in the SiO₂.
2. Remove the Co outside the contact openings by lift-off. For Co it was found that tetrahydrofuran (THF) gives the best lift-off results and growth at low temperatures. N-methyl-2-pyrrolidone (NMP), which was previously used for lift-off after Fe evaporation, was found to damage the Co too such an extent to prevent any aligned CNT growth. Put the wafer for 15 min in an ultrasonic bath with THF at 35 °C. Rinse with DI water for 5 min and dry using a spinner or nitrogen gun.
3. Inspect the wafer underneath a microscope and check for resist residues. If residues remain perform a longer ultrasonic treatment in THF, and optionally use a special soft cotton swab for lift-off purposes to manually wipe away residues.
4. Perform CNT growth using low-pressure chemical vapor deposition (LPCVD). Use the following recipe: 8 min pre-anneal at 350 °C with 700 sccm H₂ at 80 mbar, followed by CNT growth by adding 50 sccm C₂H₂. At 350 °C, 60 min of growth gives roughly 1 µm of CNT. If necessary perform a test growth to tune the height, which should be the same thickness as the SiO₂ layer. Cool down the reactor and purge using N₂.
5. Use a scanning electron microscope to check the height of the CNT inside the openings under 45° tilt, or by preparing a cross-section.
6. Inspect the samples using Raman spectroscopy to determine the crystallinity of the CNT¹⁸.

4. Topside Metallization

1. Use magnetron sputtering to deposit the top metal. As Ti is a good metal for contacting CNT¹⁹, first sputter 100 nm of Ti, followed by 2 µm of Al (1% Si) without breaking the vacuum.
2. Coat the wafer with 3.1 µm of positive photoresist with higher viscosity, starting with a 90 sec HMDS treatment at 130 °C, followed by cooling of the wafer on a cold plate, spin-coating at 3,000 rpm, and a 90 sec soft bake at 95 °C.
3. Using a photo-lithography mask and exposure tool expose the top metal pattern aligned to the alignment markers, exposure dose 420 mJ/cm², focus of -1.
4. Perform a single puddle development process. This starts with a 90 sec 115 °C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 °C.
5. Use a microscope to inspect if the lines in the resist are of the correct dimensions and if the overlay to the markers is correct.
6. Etch the Ti/Al stack using chlorine plasma etching. For example using an inductive coupled plasma: 30/40 sccm Cl₂/HBr, 5 mTorr, 40/500 W Platen/ICP RF power with endpoint detection and 80% overetch using 15/30 sccm Cl₂/HBr.
7. Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O₂ with endpoint detection and 2 min overetch). If the metal coverage is not complete (i.e., there are pinholes around the CNT) use an organic solvent (e.g., NMP) to remove the photoresist in order to prevent plasma damage to the CNT.
8. Clean the wafers. Put them for 10 min in 99% HNO₃, followed by rinsing with DI water till the resistivity of the water is 5 MΩ (organic clean). Use a rinser dryer to dry the wafers.

5. Measurements

1. Use a scanning electron microscope according to manufacturer's instructions to check the top metallization of the wafers.
   Note: If necessary the wafer can be mechanically cleaved in order to check the complete CNT via using a sample tilt of 90°, resulting in images as shown in Figure 3. As the samples are electrically conductive no additional treatment steps have to be used and the samples can be directly mounted into the SEM. Generally, high acceleration voltages of 15 or 20 kV can be used, but if the SiO₂ layer is charging up too much this can be reduced to 5 kV.
2. Perform 4-point probe I-V measurements using a probe station in combination with a semiconductor parameter analyzer as described in Figure 1 and in Vollebregt et al. ¹⁶.
   Note: Normally a voltage sweep from -0.5 to 0.5 V is sufficient, as the potential drop over an interconnect ideally is small. By using a 4-point probe setup the contact resistance of the probe needles and the wire resistances of the setup are omitted.

Wyniki

The design of the measurement structure used in this work can be found in Figure 1. By employing such a structure the measurement of the CNT bundle resistance and the metal-CNT contact resistances can be determined accurately, as probe and wire resistances are circumvented. The resistance of the bundle is a measure for the quality and density of the CNT bundle. In order to determine the contact resistance bundles of different lengths should be measured.

A typical SEM image of ...

Dyskusje

Figure 1 displays a schematic overview of the structure fabricated in this work, and which was used for the 4-point probe measurements. As the potential is measured through probes carrying no current, the exact potential drop (V_H-V_L) over the central CNT bundle and its contacts to the metal can be measured. Bigger diameter CNT bundles are used to contact the bottom TiN layer from the contact pads, in order to reduce the total resistance for the current forcing probes and maximize th...

Materiały

Name	Company	Catalog Number	Comments
Si (100) wafer 4"	International Wafer Service		Resisitivity: 2-5 mΩ-cm, thickness: 525 µm
Ti-sputter target (99.995% purity)	Praxair
Al (1% Si)-sputter target (99.999% purity)	Praxair
Co (99.95% purity)	Kurt J. Lesker
SPR3012 positive photoresist	Dow Electronic Materials
MF-322 developer	Dow Electronic Materials
HNO3 (99.9%)	KMG Ultra Pure Chemicals
HNO3 (69.5%)	KMG Ultra Pure Chemicals
HF 0.55%	Honeywell
Tetrahydrofuran	JT Baker
Acetone	Sigma-Aldrich
ECI3027 positive photoresist	AZ
Tetraethyl orthosilicate (TEOS)	Praxair
N2 (99.9990%)	Praxair
O2 (99.9999%)	Praxair
CF4 (99.9970%)	Praxair
Cl2 (99.9900%)	Praxair
HBr (99.9950%)	Praxair
Ar (99.9990%)	Praxair
C2F6 (99.9990%)	Praxair
CHF3 (99.9950%)	Praxair
H2 (99.9950%)	Praxair
C2H2 (99.6000%)	Praxair
EVG 120 coater/developer	EVG
ASML PAS5500/80 waferstepper	ASML
SPTS Ωmega 201 plasma etcher	SPTS		Used for Si and metal etching
SPTS Σigma sputter coater	SPTS
Novellus Concept One PECVD	LAM
Drytek 384T plasma etcher	LAM		Used for oxide etching
CHA Solution e-beam evaporator	CHA
AIXTRON BlackMagic Pro CVD tool	AIXTRON		Carbon nanotube growth
Philips XL50 scanning electron microscope	FEI
Tepla 300	PVA TePla		Resist plasma stripper
Avenger rinser dryer	Microporcess Technologies
Leitz MPV-SP reflecometer	Leitz
Renishaw inVia Raman spectroscope	Renishaw
Agilent 4156C parameter spectrum analyzer	Agilent
Cascade Microtech probe station	Cascade Microtech