Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Attenzione: Si prega di consultare tutte le schede di sicurezza pertinenti (MSDS) prima dell&#39;uso. Molti dei prodotti chimici utilizzati in questo processo di fabbricazione sono altamente tossici e cancerogeni. I nanomateriali possono avere rischi aggiuntivi rispetto alla loro controparte massa. Si prega di utilizzare tutte le pratiche di sicurezza appropriate quando si lavora con attrezzature, prodotti chimici o nanomateriali, compreso l&#39;uso di controlli tecnici (cappa) e dispositivi di protezione individuale (occhiali, guanti, abiti camere bianche). 1. Allineamento Marker Definizione per litografia <ol><li> Inizia con grado industriale lucido single-sided Si (100) wafer con o n o drogaggio di tipo p. </li><li> Rivestire la cialda con 1,4 micron di photoresist positivo. Eseguire 90 sec esametildisilazano (HMDS) trattamento a 130 ° C per favorire l&#39;adesione del fotoresist, seguita da raffreddamento della fetta su un piatto freddo, spin-coating ad una velocità appropriata (3500 rpm), e 90 sec bake morbido unt 95 ° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione esporre i segni di allineamento, dose di esposizione di 120 mJ / cm 2. </li><li> Eseguire un unico processo di sviluppo pozzanghera. Eseguire un 90 sec 115 ° C post-esposizione cuocere, seguito da 60 secondi di sviluppo utilizzando sviluppatore e 90 sec duro cuocere in forno a 100 ° C per curare il resistere. </li><li> Utilizzare un microscopio per controllare se le aperture di resist sono delle dimensioni corrette. </li><li> Etch 120 nm di Si utilizza plasma etching cloro. Questo spessore dà un buon contrasto per i sistemi di allineamento automatico dell&#39;utensile esposizione utilizzato in questo lavoro. Ad esempio, utilizzando un plasma ad accoppiamento induttivo (ICP): 20/40 sccm O 2 / CF 4, 5 mTorr, 60/500 W piastra / potenza RF ICP, 10 sec ossido svolta incisione, seguita da 80/40 SCCM Cl 2 / HBr , 60 mTorr, 20/500 W piastra / potenza ICP RF, 35 sec Si etch. </li><li> Utilizzare una spogliarellista plasma di ossigeno per rimuovere il photoresist (1 kW, 400 SCCM O 2 con endpoint rilevazione e 2 min overetch). Poiché il photoresist è curata da solvente come acetone plasma normale non può essere utilizzato. </li><li> Pulire i wafer. Prima metterli per 10 min a 99% HNO 3, seguita da risciacquo in acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (pulito organica). Dopo questo pulito i wafer per 10 min a 65% HNO 3 a 110 ° C, seguita da risciacquo con acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (metallo pulito). Utilizzare un essiccatore sciacquatrice per asciugare i wafer. </li></ol> 2. inferiore in metallo e strato intermedio dielettrico Deposizione <ol><li> Utilizzare magnetron sputtering a depositare lo strato metallico fondo del test via. Una pila di tre strati metallici deve essere depositato: 500 nm di Ti, 50 nm di TiN e 100 nm Ti. Il primo strato di Ti è quello di ridurre la resistenza della pila, TiN è lo strato di supporto effettivo per la crescita CNT, e la parte superiore Ti è proteggere il TiN contro danni plasma quando attacco dello strato 12 SiO 2 </sup&gt;. Eseguire Ti sputtering utilizzando un target puro Ti con Ar-plasma ad una temperatura del substrato di 350 ° C. Per TiN sputtering reattivo utilizzare una combinazione di Ar e N 2, di nuovo a 350 ° C di temperatura del substrato. </li><li> Utilizzando deposizione di vapore chimico plasma (PECVD), depositare uno spesso strato di SiO 2 1 micron. Qui tetraetilortosilicato (TEOS) viene utilizzato come precursore ad una temperatura della piastra di 350 ° C. <ol><li> Controllare lo spessore dello strato di SiO 2 utilizzando uno strumento appropriato, per esempio un riflettometro o ellissometro. </li></ol></li><li> Coat il wafer con 1,4 micron di photoresist positivo, iniziando con un trattamento 90 sec HMDS a 130 ° C, seguita da raffreddamento della fetta su un piatto freddo, spin-coating ad una velocità appropriata (3500 rpm), e 90 sec morbido cuocere in forno a 95 ° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione, esporre il modello desiderato di aperture, che verrà successivamente inciso nella SiO 2 to formare le vias, allineati per i segni di allineamento, dose di esposizione di 140 mJ / cm 2. </li><li> Eseguire un unico processo di sviluppo pozza a partire da un 90 sec 115 ° C post-esposizione bake, seguito da 60 sec sviluppo utilizzando sviluppatore e 90 sec duro cuocere a 100 ° C. </li><li> Utilizzare un microscopio per controllare se le aperture di resist sono delle dimensioni corrette e se la sovrapposizione per i segni di allineamento sia corretto. </li><li> Plasma etch le aperture di contatto negli SiO 2. Ad esempio, utilizzare un incisore triodo plasma con C 2 F 6 / CHF 3 36/144 sccm a 180 mTorr e 300 W di potenza RF. Se necessario, eseguire test velocità di attacco su un wafer di prova per minimizzare sopra incisione al 5% -10% nel tempo. Nota: Sebbene il Ti è resistente all&#39;attacco reattivo in questa chimica fluoro, prolungata esposizione al plasma si tradurrà in incisione fisica dello strato Ti. Se lo strato di TiN è esposto al plasma questo avrà un influen negativoCE sulla crescita del CNT 12. Non utilizzare attacco umido come questo si tradurrà in troppo allargamento delle aperture, rendendo la metallizzazione in alto nella parte 4 problematico. </li><li> Rimuovere il sacrificale Ti strato dopo attacco umido in 0,55% HF per 60 sec. Dopo l&#39;incisione risciacquare i wafer con acqua deionizzata fino alla resistività dell&#39;acqua è di 5 MW e utilizzare un essiccatore sciacquatrice per asciugare i wafer. Nota: Utilizzando un microscopio può essere controllato se lo strato di Ti viene attaccato lo strato di TiN avrà un colore marrone-oro, mentre il Ti è grigio metallizzato. </li></ol> 3. Catalyst Deposizione e CNT crescita <ol><li> Evaporare 5 nm di Co usando un evaporatore e-beam. Pump down fino almeno 2x10 -6 Torr, e riscaldare i wafer a 60 ° C con lampade sotto vuoto prima di depositare per rimuovere qualsiasi pellicola d&#39;acqua. La foto-resist utilizzato per definire le aperture di contatto viene mantenuto sul wafer di fornire auto-allineamento del catalizzatore alle aperture di contatto negli SiO 2. </li><li> Rimuovereil Co di fuori delle aperture di contatto con l&#39;ascensore-off. Per Co si è constatato che tetraidrofurano (THF) dà i risultati migliori lift-off e la crescita a basse temperature. N-metil-2-pirrolidone (NMP), che è stato utilizzato in precedenza per il decollo dopo Fe evaporazione, è stato trovato per danni un Co troppo misura tale da impedire qualsiasi crescita CNT allineati. Mettere il wafer per 15 min in un bagno ad ultrasuoni con THF a 35 ° C. Risciacquare con acqua deionizzata per 5 minuti e asciugare con un filatore o azoto pistola. </li><li> Controllare il wafer sotto un microscopio e verificare la presenza di residui di resistere. Qualora i residui rimangono eseguire un trattamento più lungo ultrasuoni in THF, e facoltativamente utilizzare uno speciale tampone di cotone morbido per scopi lift-off per pulire manualmente via residui. </li><li> Eseguire la crescita CNT con bassa pressione deposizione di vapore chimico (LPCVD). Utilizzare la seguente ricetta: 8 min pre-ricottura a 350 ° C con 700 SCCM H 2 a 80 mbar, seguita da una crescita CNT aggiungendo 50 sccm C 2 H 2. A 350 ° C, 60min di crescita dà circa 1 micron di CNT. Se necessario eseguire un test di crescita per sintonizzare l&#39;altezza, che dovrebbe essere lo stesso spessore dello strato di SiO 2. Far raffreddare il reattore e spurgare con N 2. </li><li> Utilizzare un microscopio elettronico a scansione per controllare l&#39;altezza del CNT all&#39;interno delle aperture sotto i 45 ° di inclinazione, oppure preparando una sezione trasversale. </li><li> Controllare i campioni utilizzando la spettroscopia Raman per determinare la cristallinità della CNT 18. </li></ol> 4. Fesa Metallizzazione <ol><li> Utilizzare magnetron sputtering per depositare il metallo in alto. Come Ti è un buon contatto metallo CNT 19, primo sputter 100 nm di Ti, seguito da 2 micron di Al (1% Si) senza rompere il vuoto. </li><li> Coat il wafer con 3,1 micron di photoresist positivo con una maggiore viscosità, iniziando con un trattamento 90 sec HMDS a 130 ° C, seguita da raffreddamento della fetta su un piatto freddo, spin-coating a 3.000 rpm, e una cottura morbida 90 sec a 95° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione esporre il metallo modello top allineati ai segni di allineamento, dose di esposizione 420 mJ / cm 2, messa a fuoco di -1. </li><li> Eseguire un unico processo di sviluppo pozzanghera. Questo inizia con un 90 sec 115 ° C post-esposizione bake, seguito da 60 sec sviluppo utilizzando sviluppatore e 90 sec duro cuocere a 100 ° C. </li><li> Utilizzare un microscopio per controllare se le linee di resist sono delle dimensioni corrette e se la sovrapposizione dei marcatori è corretta. </li><li> Etch lo stack Ti / Al mediante plasma etching cloro. Ad esempio, utilizzando un plasma ad accoppiamento induttivo: 30/40 sccm Cl 2 / HBr, 5 mTorr, 40/500 W di potenza Platen / ICP RF con rilevamento degli endpoint e l&#39;80% con 15/30 sccm overetch Cl 2 / HBr. </li><li> Utilizzare una spogliarellista plasma di ossigeno per rimuovere il photoresist (1 kW, 400 SCCM O 2 con rilevamento degli endpoint e 2 min overetch). Se la copertura metallica non è completo (cioè ci sono fori intornoCNT) utilizzare un solvente organico (ad esempio, NMP) per rimuovere il fotoresist per evitare danni plasma al CNT. </li><li> Pulire i wafer. Messo loro per 10 min a 99% HNO 3, seguito da risciacquo con acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (pulito organica). Utilizzare un essiccatore sciacquatrice per asciugare i wafer. </li></ol> 5. Misurazioni <ol><li> Utilizzare un microscopio elettronico a scansione in base alle istruzioni del produttore per verificare la metallizzazione superiore del wafer. Nota:. Se necessario, il wafer può essere scisso meccanicamente al fine di verificare la completa CNT tramite utilizzando una inclinazione campione di 90 °, per immagini, come mostrato in Figura 3 Come campioni sono elettricamente conduttivi devono essere utilizzati senza trattamenti addizionali e i campioni possono essere montati nel SEM. Generalmente, elevate tensioni di accelerazione di 15 kV o 20 possono essere utilizzate, ma se lo strato SiO 2 è in carica troppo questo può essere ridotto to 5 kV. </li><li> Eseguire 4 punti misurazioni sonda IV, per una stazione di prova in combinazione con un analizzatore di parametri a semiconduttore come descritto nella Figura 1 e in Vollebregt et al. 16. Nota: Normalmente una spazzata tensione da -0.5 a 0.5 V è sufficiente, come la caduta di potenziale tramite una interconnessione ideale è piccola. Utilizzando una configurazione sonda 4-punto la resistenza di contatto degli aghi della sonda e le resistenze a filo del setup vengono omessi. </li></ol>

<ol>
	<li>Sun, S. C. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Process+technologies+for+advanced+metallization+and+interconnect+systems.">Process technologies for advanced metallization and interconnect systems.</a> Technical digest of the IEEE International Electron Devices Meeting. , 765-768 (1997).</li><li>Robertson, J. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Growth+of+nanotubes+for+electronics.">Growth of nanotubes for electronics.</a> Mater. Today. 10 (1-2), 36-43 (2007).</li><li>Wei, B. Q., Vajtai, R., Ajayan, P. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Reliability+and+current+carrying+capacity+of+carbon+nanotubes.">Reliability and current carrying capacity of carbon nanotubes.</a> Appl. Phys. Lett. 79 (8), 1172-1174 (2001).</li><li>Rossnagel, S. M., Wisnieff, R., Edelstein, D., Kuan, T. S. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Interconnect+issues+post+45nm.">Interconnect issues post 45nm.</a> Technical digest of the IEEE International Electron Devices Meeting. , 89-91 (2005).</li><li>Pop, E., Mann, D., Wang, Q., Goodson, K., Dai, H. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Thermal+Conductance+of+an+Individual+Single-Wall+Carbon+Nanotube+above+Room+Temperature.">Thermal Conductance of an Individual Single-Wall Carbon Nanotube above Room Temperature.</a> Nano Lett. 6 (1), 96-100 (2006).</li><li>Chiodarelli, N., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Measuring+the+electrical+resistivity+and+contact+resistance+of+vertical+carbon+nanotube+bundles+for+application+as+interconnects.">Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects.</a> Nanotechnology. 22 (8), 085302 (2011).</li><li>Choi, Y. -. M., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Integration+and+Electrical+Properties+of+Carbon+Nanotube+Array+for+Interconnect+Applications.">Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications.</a> Proceedings of the Sixth IEEE Conference on Nanotechnology. , 262-265 (2006).</li><li>Dijon, J., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Ultra-high+density+Carbon+Nanotubes+on+Al-Cu+for+advanced+Vias.">Ultra-high density Carbon Nanotubes on Al-Cu for advanced Vias.</a> Technical digest of the IEEE International Electron Devices Meeting. , 33-34 (2010).</li><li>Kreupl, F., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Carbon+nanotubes+in+interconnect+applications.">Carbon nanotubes in interconnect applications.</a> Microelectron. Eng. 64 (1-4), 399-408 (2002).</li><li>Vereecke, B., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Characterization+of+carbon+nanotube+based+vertical+interconnects.">Characterization of carbon nanotube based vertical interconnects.</a> Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials. , 648-649 (2012).</li><li>Vollebregt, S., Ishihara, R., Derakhshandeh, J., vander Cingel, J., Schellevis, H., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Integrating+low+temperature+aligned+carbon+nanotubes+as+vertical+interconnects+in+Si+technology.">Integrating low temperature aligned carbon nanotubes as vertical interconnects in Si technology.</a> Proceedings of the 11th IEEE Conference on Nanotechnology. , 985-990 (2011).</li><li>Yokoyama, D., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Electrical+Properties+of+Carbon+Nanotubes+Grown+at+a+Low+Temperature+for+Use+as+Interconnects.">Electrical Properties of Carbon Nanotubes Grown at a Low Temperature for Use as Interconnects.</a> Jpn J. App. Phys. 47 (4), 1985-1990 (2008).</li><li>Van der Veen, M. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Electrical+Improvement+of+CNT+Contacts+with+Cu+Damascene+Top+Metallization.">Electrical Improvement of CNT Contacts with Cu Damascene Top Metallization.</a> Proceedings of the IEEE International Interconnect Technology Conference. , 193-195 (2013).</li><li>Istratov, A. A., Hieslmair, H., Weber, E. R. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Iron+contamination+in+silicon+technology.">Iron contamination in silicon technology.</a> Appl. Phys. A. 70, 489-534 (2000).</li><li>Vollebregt, S., Tichelaar, F. D., Schellevis, H., Beenakker, C. I. M., Ishihara, R. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Carbon+nanotube+vertical+interconnects+fabricated+at+temperatures+as+low+as+350+&#176;C.">Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 &#176;C.</a> 71, 249-256 (2014).</li><li>Kikkawa, T., Inoue, K., Imai, K. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Cobalt+silicide+technology.">Cobalt silicide technology.</a> Silicide Technology for Integrated Circuits. , 77-94 (2004).</li><li>Vollebregt, S., Ishihara, R., Tichelaar, F. D., Hou, Y., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Influence+of+the+growth+temperature+on+the+first+and+second-order+Raman+band+ratios+and+widths+of+carbon+nanotubes+and+fibers.">Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers.</a> Carbon. 50 (10), 3542-3554 (2012).</li><li>Lim, S. C., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Contact+resistance+between+metal+and+carbon+nanotube+interconnects:+Effect+of+work+function+and+wettability.">Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability.</a> Appl. Phys. Lett. 95 (26), 264103 (2009).</li><li>Awano, Y., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Carbon+nanotube+via+interconnect+technologies:+size-classified+catalyst+nanoparticles+and+low-resistance+ohmic+contact+formation.">Carbon nanotube via interconnect technologies: size-classified catalyst nanoparticles and low-resistance ohmic contact formation.</a> Phys. Status Solidi (a). 203 (14), 3611-3616 (2006).</li><li>Van der Veen, M. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Electrical+characterization+of+CNT+contacts+with+Cu+Damascene+top+contact.">Electrical characterization of CNT contacts with Cu Damascene top contact.</a> Microelectron. Eng. 106, 106-111 (2012).</li><li>Horibe, M., Nihei, M., Kondo, D., Kawabata, A., Awano, Y. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Mechanical+Polishing+Technique+for+Carbon+Nanotube+Interconnects+in+ULSIs.">Mechanical Polishing Technique for Carbon Nanotube Interconnects in ULSIs.</a> Jpn J. App. Phys. 43 (9A), 6499-6502 (2004).</li><li>Vollebregt, S., Chiaramonti, A. N., Ishihara, R., Schellevis, H., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Contact+resistance+of+low-temperature+carbon+nanotube+vertical+interconnects.">Contact resistance of low-temperature carbon nanotube vertical interconnects.</a> Proceedings of the 12th IEEE Conference on Nanotechnology. , 424-428 (2012).</li><li>Fiorentino, G., Vollebregt, S., Tichelaar, F. D., Ishihara, R., Sarro, P. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Impact+of+the+atomic+layer+deposition+precursors+diffusion+on+solid-state+carbon+nanotube+based+supercapacitors+performances.">Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances.</a> Nanotechnology. 26 (6), 064002 (2015).</li></ol>

The authors have nothing to disclose.

Figura 1 mostra una visione schematica della struttura fabbricata in questo lavoro, e che è stato utilizzato per le misurazioni della sonda 4 punti. Poiché il potenziale è misurata mediante sonde trasportano nessuna corrente, l&#39;esatta caduta di potenziale (V -V H L) sul fascio CNT centrale e suoi contatti al metallo può essere misurata. Diametro maggiore CNT fasci vengono utilizzati per contattare lo strato TiN fondo dalle piazzole di contatto, al fine di ridurre la resistenza totale ...

Il rame e tungsteno, i metalli che vengono attualmente utilizzati per le interconnessioni nella tecnologia state-of-the-art molto su larga scala di integrazione (VLSI), si avvicinano i loro limiti fisici in termini di affidabilità e di conducibilità elettrica 1. Mentre transistori demoltiplicazione generalmente migliora le loro prestazioni, in realtà aumenta la resistenza e la densità di corrente delle interconnessioni. Ciò ha provocato interconnessioni che dominano il circuito integrato (IC) prestazioni in termini di ritardo e consumo energetico 2. I nanotubi di carbonio (CNT) sono state proposte come alternativa per Cu e W metallizzazione, soprattutto per le interconnessioni verticali (vias) come CNT possono state facilmente coltivate verticale 3. CNT hanno dimostrato di avere un&#39;ottima affidabilità elettrica, permettendo una fino a 1.000 volte superiore densità di corrente di Cu 4. Inoltre, CNT non soffrono di superficie e grano dispersione di confine, che è in aumento il resistivity di Cu su scala nanometrica 5. Infine, CNT hanno dimostrato di essere ottimi conduttori termici 6, che possono aiutare nella gestione termica in chips VLSI. Per successo dell&#39;integrazione dei CNT nella tecnologia VLSI, è importante che i processi di crescita del CNT è reso compatibile con fabbricazione di semiconduttori. Ciò richiede la crescita bassa temperatura di CNT (&lt;400 ° C) utilizzando materiali e attrezzature che sono considerati compatibili e scalabile per la produzione su larga scala. Mentre molti esempi di vias prova CNT sono state dimostrate in letteratura 7,8,9,10,11,12,13,14, la maggior parte di questi utilizzano Fe come catalizzatore che è considerato come contaminante in IC produzione di 15. Inoltre, la temperatura di crescita utilizzato in molte di queste opere è molto superiore al limite superiore di 400 ° C. Preferibilmente CNT dovrebbe anche essere coltivata inferiore a 350 ° C, al fine di consentire l&#39;integrazione con i moderni dielettrici low-kappa o flessibilesubstrati. Qui vi presentiamo un metodo scalabile per la crescita di CNT a temperature fino a 350 ° C utilizzando come catalizzatore Co 16. Questo metodo è di interesse per fabbricare differenti strutture elettriche, rappresentati allineati verticalmente CNT in circuiti integrati, che vanno da interconnessione e elettrodi di super-condensatori e dispositivi di emissione di campo. Il catalizzatore di metallo Co è spesso usato in IC di produzione per la fabbricazione di siliciuro di 17, mentre TiN è un materiale barriera spesso usato 7. Inoltre, dimostriamo un processo per la fabbricazione di vias prova CNT mentre solo utilizzando tecniche di produzione di semiconduttori standard. Con questo, vias prova CNT sono fabbricati, ispezionato da microscopia elettronica a scansione (SEM) e spettroscopia Raman, ed elettricamente caratterizzata.

<table border="0" cellpadding="0" cellspacing="0" width="905">
	<colgroup>
		<col />
		<col />
		<col />
		<col />
	</colgroup>
	<tbody>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Materials</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td style="width:291px;">Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Si (100) wafer 4&#34;</td>
			<td style="width:188px;">International Wafer Service</td>
			<td style="width:119px;"></td>
			<td>Resisitivity: 2-5 m&#937;-cm, thickness: 525 &#181;m&#160;</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Ti-sputtertarget (99.995 % purity)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Al (1% Si)-sputtertarget (99.999 % purity)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Co (99.95 % purity)</td>
			<td style="width:188px;">Kurt J. Lesker</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Chemicals</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPR3012 positive photoresist</td>
			<td style="width:188px;">Dow Electronic Materials</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">MF-322 developer</td>
			<td style="width:188px;">Dow Electronic Materials</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HNO3 (99.9 %)</td>
			<td style="width:188px;">KMG Ultra Pure Chemicals</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HNO3 (69.5%)</td>
			<td style="width:188px;">KMG Ultra Pure Chemicals</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HF 0.55%</td>
			<td style="width:188px;">Honeywell</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tetrahydrofuran</td>
			<td style="width:188px;">JT Baker</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Acetone</td>
			<td style="width:188px;">Sigma-Aldrich</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">ECI3027 positive photoresist</td>
			<td style="width:188px;">AZ</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tetraethyl orthosilicate (TEOS)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Gasses</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">N2 (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">O2 (99.9999%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CF4 (99.9970%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CL2 (99.9900%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HBr (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Ar (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">C2F6 (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CHF3 (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">H2 (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">C2H2 (99.6000%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Equipment</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">EVG 120 coater/developer</td>
			<td style="width:188px;">EVG</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">ASML PAS5500/80 waferstepper</td>
			<td style="width:188px;">ASML</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPTS &#937;mega 201 plasma etcher</td>
			<td style="width:188px;">SPTS</td>
			<td style="width:119px;"></td>
			<td>Used for Si and metal etching</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPTS &#931;igma sputter coater</td>
			<td style="width:188px;">SPTS</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Novellus Concept One PECVD</td>
			<td style="width:188px;">LAM</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Drytek 384T plasma etcher</td>
			<td style="width:188px;">LAM</td>
			<td style="width:119px;"></td>
			<td>Used for oxide etching</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CHA Solution e-beam evaporator</td>
			<td style="width:188px;">CHA</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">AIXTRON BlackMagic Pro CVD tool</td>
			<td style="width:188px;">AIXTRON</td>
			<td style="width:119px;"></td>
			<td>Carbon nanotube growth</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Philips XL50 scanning electron microscope</td>
			<td style="width:188px;">FEI</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tepla 300</td>
			<td style="width:188px;">PVA TePla</td>
			<td style="width:119px;"></td>
			<td>Resist plasma stripper</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Avenger rinser dryer</td>
			<td style="width:188px;">Microporcess Technologies</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Leitz MPV-SP reflecometer</td>
			<td style="width:188px;">Leitz</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Renishaw inVia Raman spectroscope</td>
			<td style="width:188px;">Renishaw</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Agilent 4156C parameter spectrum analyzer</td>
			<td style="width:188px;">Agilent</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Cascade Microtech probe station</td>
			<td style="width:188px;">Cascade Microtech</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
	</tbody>
</table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

Il disegno della struttura misura utilizzata in questo lavoro può essere trovato in Figura 1. Utilizzando una tale struttura la misurazione della resistenza fascio CNT e le resistenze di contatto metallo-CNT può essere determinato con precisione, come sonde e fili resistenze sono aggirate. La resistenza del fascio è una misura per la qualità e la densità del fascio CNT. Per determinare i fasci resistenza di contatto di lunghezza diversa devono essere misurati. Una tipic...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Fabbricazione di bassa temperatura Nanotubi di carbonio interconnessioni verticali Compatibile con la tecnologia Semiconductor

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Research

JoVE Journal

Engineering

7.6K Views.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Video: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

Molding Fabrication, densificazione e Replica di microstrutture 3D Nanotubi di carbonio

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

Ricerca

Ingegneria

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

Ossidazione a secco e vuoto ricottura Trattamenti per accordare le proprietà di bagnabilità di matrici di nanotubi di carbonio

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Synthesis and Functionalization of Nitrogen-doped Carbon Nanotube Cups with Gold Nanoparticles as Cork Stoppers

Nitrogen-doped carbon nanotubes consist of many cup-shaped graphitic compartments termed as nitrogen-doped carbon nanotube cups (NCNCs). These as-synthesized graphitic nanocups from chemical vapor deposition (CVD) method were stacked in a head-to-tail fashion held only through noncovalent interactions. Individual NCNCs can be isolated out of their stacking structure through a series of chemical and physical separation processes. First, as-synthesized NCNCs were oxidized in a mixture of strong acids to introduce oxygen-containing defects on the graphitic walls. The oxidized NCNCs were then processed using high-intensity probe-tip sonication which effectively separated the stacked NCNCs into individual graphitic nanocups. Owing to their abundant oxygen and nitrogen surface functionalities, the resulted individual NCNCs are highly hydrophilic and can be effectively functionalized with gold nanoparticles (GNPs), which preferentially fit in the opening of the cups as cork stoppers. These graphitic nanocups corked with GNPs may find promising applications as nanoscale containers and drug carriers.

We discussed the synthesis of individual graphitic nanocups using a series of techniques including chemical vapor deposition, acid oxidation and probe-tip sonication. By citrate reduction of HAuCl4, the graphitic nanocups were effectively corked with gold nanoparticles due to the chemically reactive edges of the cups.

Sintesi e funzionalizzazione di azoto drogati Coppe nanotubi di carbonio con nanoparticelle di oro come tappi di sughero

Nitrogen-doped carbon  nanotubes consist of many cup-shaped graphitic compartments termed as  nitrogen-doped carbon nanotube cups (NCNCs).  These ...

Writing and Low-Temperature Characterization of Oxide Nanostructures

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions. Oxide interfaces exhibit a wide range of properties that can be controlled include conduction, piezoelectric behavior, ferromagnetism, superconductivity and nonlinear optical properties. Recently, methods for controlling these properties at extreme nanoscale dimensions have been discovered and developed. Here are described explicit step-by-step procedures for creating LaAlO3/SrTiO3 nanostructures using a reversible conductive atomic force microscopy technique. The processing steps for creating electrical contacts to the LaAlO3/SrTiO3 interface are first described. Conductive nanostructures are created by applying voltages to a conductive atomic force microscope tip and locally switching the LaAlO3/SrTiO3 interface to a conductive state. A versatile nanolithography toolkit has been developed expressly for the purpose of controlling the atomic force microscope (AFM) tip path and voltage. Then, these nanostructures are placed in a cryostat and transport measurements are performed. The procedures described here should be useful to others wishing to conduct research in oxide nanoelectronics.

Oxide nanostructures provide new opportunities for science and technology. The interfacial conductivity between LaAlO3 and SrTiO3 can be controlled with near-atomic precision using a conductive atomic force microscopy technique. The protocol for creating and measuring conductive nanostructures at LaAlO3/SrTiO3 interfaces is demonstrated.

Scrittura e bassa temperatura Caratterizzazione di nanostrutture di ossido

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions.  Oxide ...

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal&#8211;semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 &#937;&#8722;1 cm&#8722;1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

We describe the approaches for the device fabrication and electrical characterization of molybdenum diselenide (MoSe2) layer semiconductor nanostructures with different thicknesses. In addition, the fabrication of ohmic contacts for MoSe2-layer nanocrystals by the focused-ion beam deposition method using platinum (Pt) as a contact metal is described.

Ohmico Fabrication contatto con una tecnica Focused Ion Beam-e caratterizzazione elettrica per strato semiconduttore Nanostrutture

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor ...

Advanced Experimental Methods for Low-temperature Magnetotransport Measurement of Novel Materials

Novel electronic materials are often produced for the first time by synthesis processes that yield bulk crystals (in contrast to single crystal thin film synthesis) for the purpose of exploratory materials research. Certain materials pose a challenge wherein the traditional bulk Hall bar device fabrication method is insufficient to produce a measureable device for sample transport measurement, principally because the single crystal size is too small to attach wire leads to the sample in a Hall bar configuration. This can be, for example, because the first batch of a new material synthesized yields very small single crystals or because flakes of samples of one to very few monolayers are desired. In order to enable rapid characterization of materials that may be carried out in parallel with improvements to their growth methodology, a method of device fabrication for very small samples has been devised to permit the characterization of novel materials as soon as a preliminary batch has been produced. A slight variation of this methodology is applicable to producing devices using exfoliated samples of two-dimensional materials such as graphene, hexagonal boron nitride (hBN), and transition metal dichalcogenides (TMDs), as well as multilayer heterostructures of such materials. Here we present detailed protocols for the experimental device fabrication of fragments and flakes of novel materials with micron-sized dimensions onto substrate and subsequent measurement in a commercial superconducting magnet, dry helium close-cycle cryostat magnetotransport system at temperatures down to 0.300 K and magnetic fields up to 12 T.

We describe the methodology of mechanical exfoliation and deposition of flakes of novel materials with micron-sized dimensions onto substrate, fabrication of experimental device structures for transport experimentation, and the magnetotransport measurement in a dry helium close-cycle cryostat at temperatures down to 0.300 K and magnetic fields up to 12 T.

Metodi sperimentali avanzati per bassa temperatura magnetotrasporto Misura di nuovi materiali

Novel electronic materials are often produced for the first time by synthesis processes that yield bulk crystals (in contrast to single crystal thin film ...

Precision Milling of Carbon Nanotube Forests Using Low Pressure Scanning Electron Microscopy

A nanoscale fabrication technique appropriate for milling carbon nanotube (CNT) forests is described. The technique utilizes an environmental scanning electron microscope (ESEM) operating with a low pressure water vapor ambient. In this technique, a portion of the electron beam interacts with the water vapor in the vicinity of the CNT sample, dissociating the water molecules into hydroxyl radicals and other species by radiolysis. The remainder of the electron beam interacts with the CNT forest sample, making it susceptible to oxidation from the chemical products of radiolysis. This technique may be used to trim a selected region of an individual CNT, or it may be used to remove hundreds of cubic microns of material by adjusting ESEM parameters. The machining resolution is similar to the imaging resolution of the ESEM itself. The technique produces only small quantities of carbon residue along the boundaries of the cutting zone, with minimal effect on the native structural morphology of the CNT forest.

Low pressure scanning electron microscopy in a water vapor ambient is used to machine nanoscale to microscale features in carbon nanotube forests.

Precisione fresatura di Nanotubi di carbonio delle foreste Utilizzando bassa pressione Scanning Electron Microscopy

A nanoscale fabrication technique appropriate for milling carbon nanotube (CNT) forests is described. The technique utilizes an environmental scanning ...

High Temperature Fabrication of Nanostructured Yttria-Stabilized-Zirconia (YSZ) Scaffolds by In Situ Carbon Templating Xerogels

We demonstrate a method for the high temperature fabrication of porous, nanostructured yttria-stabilized-zirconia (YSZ, 8 mol% yttria - 92 mol% zirconia) scaffolds with tunable specific surface areas up to 80 m2&#183;g-1. An aqueous solution of a zirconium salt, yttrium salt, and glucose is mixed with propylene oxide (PO) to form a gel. The gel is dried under ambient conditions to form a xerogel. The xerogel is pressed into pellets and then sintered in an argon atmosphere. During sintering, a YSZ ceramic phase forms and the organic components decompose, leaving behind amorphous carbon. The carbon formed in situ serves as a hard template, preserving a high surface area YSZ nanomorphology at sintering temperature. The carbon is subsequently removed by oxidation in air at low temperature, resulting in a porous, nanostructured YSZ scaffold. The concentration of the carbon template and the final scaffold surface area can be systematically tuned by varying the glucose concentration in the gel synthesis. The carbon template concentration was quantified using thermogravimetric analysis (TGA), the surface area and pore size distribution was determined by physical adsorption measurements, and the morphology was characterized using scanning electron microscopy (SEM). Phase purity and crystallite size was determined using X-ray diffraction (XRD). This fabrication approach provides a novel, flexible platform for realizing unprecedented scaffold surface areas and nanomorphologies for ceramic-based electrochemical energy conversion applications, e.g. solid oxide fuel cell (SOFC) electrodes.

High Temperature Fabrication of Nanostructured Yttria-Stabilized-Zirconia YSZ Scaffolds by In Situ Carbon Templating Xerogels

A protocol for fabricating porous, nanostructured yttria-stabilized-zirconia (YSZ) scaffolds at temperatures between 1,000 &#176;C and 1,400 &#176;C is presented.

Fabbricazione ad alta temperatura di Nanostrutturati di ossido di ittrio stabilizzato-Zirconia (YSZ) Ponteggi da<em&gt; In Situ</em&gt; Carbon Templating xerogel

We demonstrate a method for the high temperature fabrication of porous, nanostructured yttria-stabilized-zirconia (YSZ, 8 mol% yttria - 92 mol% zirconia) ...

Fabrication of 3D Carbon Microelectromechanical Systems (C-MEMS)

A wide range of carbon sources are available in nature, with a variety of micro-/nanostructure configurations. Here, a novel technique to fabricate long and hollow glassy carbon microfibers derived from human hairs is introduced. The long and hollow carbon structures were made by the pyrolysis of human hair at 900 &#176;C in a N2 atmosphere. The morphology and chemical composition of natural and pyrolyzed human hairs were investigated using scanning electron microscopy (SEM) and electron-dispersive X-ray spectroscopy (EDX), respectively, to estimate the physical and chemical changes due to pyrolysis. Raman spectroscopy was used to confirm the glassy nature of the carbon microstructures. Pyrolyzed hair carbon was introduced to modify screen-printed carbon electrodes ; the modified electrodes were then applied to the electrochemical sensing of dopamine and ascorbic acid. Sensing performance of the modified sensors was improved as compared to the unmodified sensors. To obtain the desired carbon structure design, carbon micro-/nanoelectromechanical system (C-MEMS/C-NEMS) technology was developed. The most common C-MEMS/C-NEMS fabrication process consists of two steps: (i) the patterning of a carbon-rich base material, such as a photosensitive polymer, using photolithography; and (ii) carbonization through the pyrolysis of the patterned polymer in an oxygen-free environment. The C-MEMS/NEMS process has been widely used to develop microelectronic devices for various applications, including in micro-batteries, supercapacitors, glucose sensors, gas sensors, fuel cells, and triboelectric nanogenerators. Here, recent developments of a high-aspect ratio solid and hollow carbon microstructures with SU8 photoresists are discussed. The structural shrinkage during pyrolysis was investigated using confocal microscopy and SEM. Raman spectroscopy was used to confirm the crystallinity of the structure, and the atomic percentage of the elements present in the material before and after pyrolysis was measured using EDX.

Fabrication of 3D Carbon Microelectromechanical Systems C-MEMS

Long and hollow glassy carbon microfibers were fabricated based on the pyrolysis of a natural product, human hair. The two fabrication steps of carbon microelectromechanical and carbon nanoelectromechanical systems, or C-MEMS and C-NEMS, are: (i) photolithography of a carbon-rich polymer precursor and (ii) pyrolysis of the patterned polymer precursor.

Fabbricazione di sistemi microelettromeccanici a carbonio 3D (C-MEMS)

A wide range of carbon sources are available in nature, with a variety of micro-/nanostructure configurations. Here, a novel technique to fabricate long ...

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flusso-assistita dielettroforesi: Un metodo a basso costo per la realizzazione di dispositivi ad alte prestazioni soluzione-processable Nanowire

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...