Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Attenzione: Si prega di consultare tutte le schede di sicurezza pertinenti (MSDS) prima dell&#39;uso. Molti dei prodotti chimici utilizzati in questo processo di fabbricazione sono altamente tossici e cancerogeni. I nanomateriali possono avere rischi aggiuntivi rispetto alla loro controparte massa. Si prega di utilizzare tutte le pratiche di sicurezza appropriate quando si lavora con attrezzature, prodotti chimici o nanomateriali, compreso l&#39;uso di controlli tecnici (cappa) e dispositivi di protezione individuale (occhiali, guanti, abiti camere bianche). 1. Allineamento Marker Definizione per litografia <ol><li> Inizia con grado industriale lucido single-sided Si (100) wafer con o n o drogaggio di tipo p. </li><li> Rivestire la cialda con 1,4 micron di photoresist positivo. Eseguire 90 sec esametildisilazano (HMDS) trattamento a 130 ° C per favorire l&#39;adesione del fotoresist, seguita da raffreddamento della fetta su un piatto freddo, spin-coating ad una velocità appropriata (3500 rpm), e 90 sec bake morbido unt 95 ° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione esporre i segni di allineamento, dose di esposizione di 120 mJ / cm 2. </li><li> Eseguire un unico processo di sviluppo pozzanghera. Eseguire un 90 sec 115 ° C post-esposizione cuocere, seguito da 60 secondi di sviluppo utilizzando sviluppatore e 90 sec duro cuocere in forno a 100 ° C per curare il resistere. </li><li> Utilizzare un microscopio per controllare se le aperture di resist sono delle dimensioni corrette. </li><li> Etch 120 nm di Si utilizza plasma etching cloro. Questo spessore dà un buon contrasto per i sistemi di allineamento automatico dell&#39;utensile esposizione utilizzato in questo lavoro. Ad esempio, utilizzando un plasma ad accoppiamento induttivo (ICP): 20/40 sccm O 2 / CF 4, 5 mTorr, 60/500 W piastra / potenza RF ICP, 10 sec ossido svolta incisione, seguita da 80/40 SCCM Cl 2 / HBr , 60 mTorr, 20/500 W piastra / potenza ICP RF, 35 sec Si etch. </li><li> Utilizzare una spogliarellista plasma di ossigeno per rimuovere il photoresist (1 kW, 400 SCCM O 2 con endpoint rilevazione e 2 min overetch). Poiché il photoresist è curata da solvente come acetone plasma normale non può essere utilizzato. </li><li> Pulire i wafer. Prima metterli per 10 min a 99% HNO 3, seguita da risciacquo in acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (pulito organica). Dopo questo pulito i wafer per 10 min a 65% HNO 3 a 110 ° C, seguita da risciacquo con acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (metallo pulito). Utilizzare un essiccatore sciacquatrice per asciugare i wafer. </li></ol> 2. inferiore in metallo e strato intermedio dielettrico Deposizione <ol><li> Utilizzare magnetron sputtering a depositare lo strato metallico fondo del test via. Una pila di tre strati metallici deve essere depositato: 500 nm di Ti, 50 nm di TiN e 100 nm Ti. Il primo strato di Ti è quello di ridurre la resistenza della pila, TiN è lo strato di supporto effettivo per la crescita CNT, e la parte superiore Ti è proteggere il TiN contro danni plasma quando attacco dello strato 12 SiO 2 </sup&gt;. Eseguire Ti sputtering utilizzando un target puro Ti con Ar-plasma ad una temperatura del substrato di 350 ° C. Per TiN sputtering reattivo utilizzare una combinazione di Ar e N 2, di nuovo a 350 ° C di temperatura del substrato. </li><li> Utilizzando deposizione di vapore chimico plasma (PECVD), depositare uno spesso strato di SiO 2 1 micron. Qui tetraetilortosilicato (TEOS) viene utilizzato come precursore ad una temperatura della piastra di 350 ° C. <ol><li> Controllare lo spessore dello strato di SiO 2 utilizzando uno strumento appropriato, per esempio un riflettometro o ellissometro. </li></ol></li><li> Coat il wafer con 1,4 micron di photoresist positivo, iniziando con un trattamento 90 sec HMDS a 130 ° C, seguita da raffreddamento della fetta su un piatto freddo, spin-coating ad una velocità appropriata (3500 rpm), e 90 sec morbido cuocere in forno a 95 ° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione, esporre il modello desiderato di aperture, che verrà successivamente inciso nella SiO 2 to formare le vias, allineati per i segni di allineamento, dose di esposizione di 140 mJ / cm 2. </li><li> Eseguire un unico processo di sviluppo pozza a partire da un 90 sec 115 ° C post-esposizione bake, seguito da 60 sec sviluppo utilizzando sviluppatore e 90 sec duro cuocere a 100 ° C. </li><li> Utilizzare un microscopio per controllare se le aperture di resist sono delle dimensioni corrette e se la sovrapposizione per i segni di allineamento sia corretto. </li><li> Plasma etch le aperture di contatto negli SiO 2. Ad esempio, utilizzare un incisore triodo plasma con C 2 F 6 / CHF 3 36/144 sccm a 180 mTorr e 300 W di potenza RF. Se necessario, eseguire test velocità di attacco su un wafer di prova per minimizzare sopra incisione al 5% -10% nel tempo. Nota: Sebbene il Ti è resistente all&#39;attacco reattivo in questa chimica fluoro, prolungata esposizione al plasma si tradurrà in incisione fisica dello strato Ti. Se lo strato di TiN è esposto al plasma questo avrà un influen negativoCE sulla crescita del CNT 12. Non utilizzare attacco umido come questo si tradurrà in troppo allargamento delle aperture, rendendo la metallizzazione in alto nella parte 4 problematico. </li><li> Rimuovere il sacrificale Ti strato dopo attacco umido in 0,55% HF per 60 sec. Dopo l&#39;incisione risciacquare i wafer con acqua deionizzata fino alla resistività dell&#39;acqua è di 5 MW e utilizzare un essiccatore sciacquatrice per asciugare i wafer. Nota: Utilizzando un microscopio può essere controllato se lo strato di Ti viene attaccato lo strato di TiN avrà un colore marrone-oro, mentre il Ti è grigio metallizzato. </li></ol> 3. Catalyst Deposizione e CNT crescita <ol><li> Evaporare 5 nm di Co usando un evaporatore e-beam. Pump down fino almeno 2x10 -6 Torr, e riscaldare i wafer a 60 ° C con lampade sotto vuoto prima di depositare per rimuovere qualsiasi pellicola d&#39;acqua. La foto-resist utilizzato per definire le aperture di contatto viene mantenuto sul wafer di fornire auto-allineamento del catalizzatore alle aperture di contatto negli SiO 2. </li><li> Rimuovereil Co di fuori delle aperture di contatto con l&#39;ascensore-off. Per Co si è constatato che tetraidrofurano (THF) dà i risultati migliori lift-off e la crescita a basse temperature. N-metil-2-pirrolidone (NMP), che è stato utilizzato in precedenza per il decollo dopo Fe evaporazione, è stato trovato per danni un Co troppo misura tale da impedire qualsiasi crescita CNT allineati. Mettere il wafer per 15 min in un bagno ad ultrasuoni con THF a 35 ° C. Risciacquare con acqua deionizzata per 5 minuti e asciugare con un filatore o azoto pistola. </li><li> Controllare il wafer sotto un microscopio e verificare la presenza di residui di resistere. Qualora i residui rimangono eseguire un trattamento più lungo ultrasuoni in THF, e facoltativamente utilizzare uno speciale tampone di cotone morbido per scopi lift-off per pulire manualmente via residui. </li><li> Eseguire la crescita CNT con bassa pressione deposizione di vapore chimico (LPCVD). Utilizzare la seguente ricetta: 8 min pre-ricottura a 350 ° C con 700 SCCM H 2 a 80 mbar, seguita da una crescita CNT aggiungendo 50 sccm C 2 H 2. A 350 ° C, 60min di crescita dà circa 1 micron di CNT. Se necessario eseguire un test di crescita per sintonizzare l&#39;altezza, che dovrebbe essere lo stesso spessore dello strato di SiO 2. Far raffreddare il reattore e spurgare con N 2. </li><li> Utilizzare un microscopio elettronico a scansione per controllare l&#39;altezza del CNT all&#39;interno delle aperture sotto i 45 ° di inclinazione, oppure preparando una sezione trasversale. </li><li> Controllare i campioni utilizzando la spettroscopia Raman per determinare la cristallinità della CNT 18. </li></ol> 4. Fesa Metallizzazione <ol><li> Utilizzare magnetron sputtering per depositare il metallo in alto. Come Ti è un buon contatto metallo CNT 19, primo sputter 100 nm di Ti, seguito da 2 micron di Al (1% Si) senza rompere il vuoto. </li><li> Coat il wafer con 3,1 micron di photoresist positivo con una maggiore viscosità, iniziando con un trattamento 90 sec HMDS a 130 ° C, seguita da raffreddamento della fetta su un piatto freddo, spin-coating a 3.000 rpm, e una cottura morbida 90 sec a 95° C. </li><li> Utilizzando una maschera di foto-litografia e strumento di esposizione esporre il metallo modello top allineati ai segni di allineamento, dose di esposizione 420 mJ / cm 2, messa a fuoco di -1. </li><li> Eseguire un unico processo di sviluppo pozzanghera. Questo inizia con un 90 sec 115 ° C post-esposizione bake, seguito da 60 sec sviluppo utilizzando sviluppatore e 90 sec duro cuocere a 100 ° C. </li><li> Utilizzare un microscopio per controllare se le linee di resist sono delle dimensioni corrette e se la sovrapposizione dei marcatori è corretta. </li><li> Etch lo stack Ti / Al mediante plasma etching cloro. Ad esempio, utilizzando un plasma ad accoppiamento induttivo: 30/40 sccm Cl 2 / HBr, 5 mTorr, 40/500 W di potenza Platen / ICP RF con rilevamento degli endpoint e l&#39;80% con 15/30 sccm overetch Cl 2 / HBr. </li><li> Utilizzare una spogliarellista plasma di ossigeno per rimuovere il photoresist (1 kW, 400 SCCM O 2 con rilevamento degli endpoint e 2 min overetch). Se la copertura metallica non è completo (cioè ci sono fori intornoCNT) utilizzare un solvente organico (ad esempio, NMP) per rimuovere il fotoresist per evitare danni plasma al CNT. </li><li> Pulire i wafer. Messo loro per 10 min a 99% HNO 3, seguito da risciacquo con acqua deionizzata fino alla resistività dell&#39;acqua è 5 MW (pulito organica). Utilizzare un essiccatore sciacquatrice per asciugare i wafer. </li></ol> 5. Misurazioni <ol><li> Utilizzare un microscopio elettronico a scansione in base alle istruzioni del produttore per verificare la metallizzazione superiore del wafer. Nota:. Se necessario, il wafer può essere scisso meccanicamente al fine di verificare la completa CNT tramite utilizzando una inclinazione campione di 90 °, per immagini, come mostrato in Figura 3 Come campioni sono elettricamente conduttivi devono essere utilizzati senza trattamenti addizionali e i campioni possono essere montati nel SEM. Generalmente, elevate tensioni di accelerazione di 15 kV o 20 possono essere utilizzate, ma se lo strato SiO 2 è in carica troppo questo può essere ridotto to 5 kV. </li><li> Eseguire 4 punti misurazioni sonda IV, per una stazione di prova in combinazione con un analizzatore di parametri a semiconduttore come descritto nella Figura 1 e in Vollebregt et al. 16. Nota: Normalmente una spazzata tensione da -0.5 a 0.5 V è sufficiente, come la caduta di potenziale tramite una interconnessione ideale è piccola. Utilizzando una configurazione sonda 4-punto la resistenza di contatto degli aghi della sonda e le resistenze a filo del setup vengono omessi. </li></ol>

<ol>
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The authors have nothing to disclose.

Figura 1 mostra una visione schematica della struttura fabbricata in questo lavoro, e che è stato utilizzato per le misurazioni della sonda 4 punti. Poiché il potenziale è misurata mediante sonde trasportano nessuna corrente, l&#39;esatta caduta di potenziale (V -V H L) sul fascio CNT centrale e suoi contatti al metallo può essere misurata. Diametro maggiore CNT fasci vengono utilizzati per contattare lo strato TiN fondo dalle piazzole di contatto, al fine di ridurre la resistenza totale ...

Il rame e tungsteno, i metalli che vengono attualmente utilizzati per le interconnessioni nella tecnologia state-of-the-art molto su larga scala di integrazione (VLSI), si avvicinano i loro limiti fisici in termini di affidabilità e di conducibilità elettrica 1. Mentre transistori demoltiplicazione generalmente migliora le loro prestazioni, in realtà aumenta la resistenza e la densità di corrente delle interconnessioni. Ciò ha provocato interconnessioni che dominano il circuito integrato (IC) prestazioni in termini di ritardo e consumo energetico 2. I nanotubi di carbonio (CNT) sono state proposte come alternativa per Cu e W metallizzazione, soprattutto per le interconnessioni verticali (vias) come CNT possono state facilmente coltivate verticale 3. CNT hanno dimostrato di avere un&#39;ottima affidabilità elettrica, permettendo una fino a 1.000 volte superiore densità di corrente di Cu 4. Inoltre, CNT non soffrono di superficie e grano dispersione di confine, che è in aumento il resistivity di Cu su scala nanometrica 5. Infine, CNT hanno dimostrato di essere ottimi conduttori termici 6, che possono aiutare nella gestione termica in chips VLSI. Per successo dell&#39;integrazione dei CNT nella tecnologia VLSI, è importante che i processi di crescita del CNT è reso compatibile con fabbricazione di semiconduttori. Ciò richiede la crescita bassa temperatura di CNT (&lt;400 ° C) utilizzando materiali e attrezzature che sono considerati compatibili e scalabile per la produzione su larga scala. Mentre molti esempi di vias prova CNT sono state dimostrate in letteratura 7,8,9,10,11,12,13,14, la maggior parte di questi utilizzano Fe come catalizzatore che è considerato come contaminante in IC produzione di 15. Inoltre, la temperatura di crescita utilizzato in molte di queste opere è molto superiore al limite superiore di 400 ° C. Preferibilmente CNT dovrebbe anche essere coltivata inferiore a 350 ° C, al fine di consentire l&#39;integrazione con i moderni dielettrici low-kappa o flessibilesubstrati. Qui vi presentiamo un metodo scalabile per la crescita di CNT a temperature fino a 350 ° C utilizzando come catalizzatore Co 16. Questo metodo è di interesse per fabbricare differenti strutture elettriche, rappresentati allineati verticalmente CNT in circuiti integrati, che vanno da interconnessione e elettrodi di super-condensatori e dispositivi di emissione di campo. Il catalizzatore di metallo Co è spesso usato in IC di produzione per la fabbricazione di siliciuro di 17, mentre TiN è un materiale barriera spesso usato 7. Inoltre, dimostriamo un processo per la fabbricazione di vias prova CNT mentre solo utilizzando tecniche di produzione di semiconduttori standard. Con questo, vias prova CNT sono fabbricati, ispezionato da microscopia elettronica a scansione (SEM) e spettroscopia Raman, ed elettricamente caratterizzata.

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

Il disegno della struttura misura utilizzata in questo lavoro può essere trovato in Figura 1. Utilizzando una tale struttura la misurazione della resistenza fascio CNT e le resistenze di contatto metallo-CNT può essere determinato con precisione, come sonde e fili resistenze sono aggirate. La resistenza del fascio è una misura per la qualità e la densità del fascio CNT. Per determinare i fasci resistenza di contatto di lunghezza diversa devono essere misurati. Una tipic...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Fabbricazione di bassa temperatura Nanotubi di carbonio interconnessioni verticali Compatibile con la tecnologia Semiconductor

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Research

JoVE Journal

Engineering

7.6K Views.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Video: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

Molding Fabrication, densificazione e Replica di microstrutture 3D Nanotubi di carbonio

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

Ricerca

Ingegneria

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

Realizzazione nanogap da Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Chimica

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

Ossidazione a secco e vuoto ricottura Trattamenti per accordare le proprietà di bagnabilità di matrici di nanotubi di carbonio

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

Altissima densità Array of allineato verticalmente Nanofili organici piccola molecolari su substrati arbitrarie

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

Produzione di tridimensionalmente microstrutturate nanocompositi attraverso Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Fabbricazione di cavità uniformi su nanoscala tramite silicon direct wafer bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

Fabbricazione di Nanotubi di carbonio ad alta frequenza Nanoelectronic biosensore per la rilevazione in alta forza ionica Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioingegneria

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flusso-assistita dielettroforesi: Un metodo a basso costo per la realizzazione di dispositivi ad alte prestazioni soluzione-processable Nanowire

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Un metodo Standard e affidabile per fabbricare nanoelettronica bidimensionale

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.