Name: fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology
Uploaded: 2015-12-07T13:00:00.000+00:00
Duration: 9 min 20 s
Description: Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

주의 : 사용하기 전에 모든 관련 물질 안전 보건 자료 (MSDS)를 참조하시기 바랍니다. 이 제조 공정에서 사용되는 화학 물질 중 일부는 급성 독성 및 발암 성이다. 나노 물질은 대량의 대응에 비해 추가 위험이있을 수 있습니다. 공학적 관리 (흄 후드) 및 개인 보호 장비 (안전 안경, 장갑, 클린 룸 의류)의 사용을 포함, 장비, 화학 물질이나 나노 물질 작업을 할 때 모든 적절한 안전 방법을 사용하십시오. 리소그래피 1. 정렬 마커 정의 <ol><li> 하나 n 또는 p 형 도핑 단일 양면 연마 산업 등급의 Si (100) 웨이퍼로 시작합니다. </li><li> 코트 긍정적 인 포토 레지스트의 1.4 μm의와 웨이퍼. 적절한 속도 (3500 RPM)에서 냉각 판, 스핀 코팅에 웨이퍼를 냉각 한 다음, 포토 레지스트의 접착을 촉진하기 위해 130 ℃에서 90 초, 헥사 메틸 디 실라 잔 (HMDS) 처리를 수행하고, 90 초간 소프트 베이크T 95 ° C를. </li><li> 포토 리소그래피 마스크를 사용하여 노광 툴은 정렬 마커를 노출, 노광량 120 mJ의 / cm 2. </li><li> 하나의 웅덩이 개발 프로세스를 수행합니다. 레지스트가 경화 100 ℃에서 90 초간 현상하고 하드 베이크를 사용하여 60 초간 현상 한 다음 90 초 115 ° C의 노광 후 베이킹을 수행. </li><li> 레지스트의 개구부가 정확한 치수의 경우 검사 현미경을 사용합니다. </li><li> Si를 염소 플라즈마 에칭을 사용하여 120 nm의 에칭. 이 두께는이 작품에 사용되는 노광 장치의 자동 정렬 시스템을위한 좋은 대조를 제공합니다. 20/40 SCCM의 O 2 / CF 4, 5 mTorr 이하, 정반 500분의 60 W / ICP RF 전력, Cl2를 40분의 80 SCCM이어서 10 초 산화물 브레이크 스루 에칭 / HBr을 : 유도 결합 형 플라즈마 (ICP)를 사용하여 예를 들어 , 60 mTorr 이하, 5백분의 20 W 정반 / ICP RF 전력, 35 초 Si의 에칭. </li><li> 포토 레지스트 (1 kW 급, endpo 400 SCCM의 O 2를 제거하기 위해 산소 플라즈마 스트리퍼를 사용하여INT 검출 및 2 분 오버 에칭). 포토 레지스트는 아세톤과 같은 플라즈마 통상 용매에 의해 경화되기 때문에 사용될 수 없다. </li><li> 웨이퍼를 청소합니다. 물의 저항은 5 MΩ (유기 청소) 될 때까지 첫 번째 DI 물에 세척 한 다음 99 % HNO 3, 10 분 동안 넣어. 물의 비저항은 5 MΩ (깨끗한 금속) 될 때까지 110 ℃에서 65 % HNO 3에서 10 분간 웨이퍼이 깨끗하게 한 후, 탈 이온수로 린스 하였다. 웨이퍼를 건조 린서 드라이어를 사용합니다. </li></ol> 2. 아래 금속 및 층간 증착 <ol><li> 비아 시험 하부 금속층을 증착하기 위해 마그네트론 스퍼터링을 사용한다. Ti를 500nm의 주석을 50 nm의, 100 nm의 티를 세 금속층 스택에 증착 될 필요가있다. 제 Ti 층 스택의 저항을 감소시키는, 주석은 CNT 성장 실제 지지층이며, SiO2의 층 (12)을 에칭 할 때 상단 TI는 플라즈마 손상에 대해 주석 보호하는 </suP&gt;. TI는 350 ℃의 기판 온도에서 아르곤 플라즈마과 순수한 티타늄의 타겟을 이용하여 스퍼터링을 수행한다. 반응성 스퍼터링 TiN을 350 ℃의 기판 온도에서 다시, 아르곤 및 N (2)의 조합을 사용한다. </li><li> 플라즈마 강화 화학 기상 증착 (PECVD)을 이용하여, SiO2로 1 μm의 두께 층을 증착. 여기에 테트라 에틸 오르토 실리케이트 (TEOS)를 350 ℃의 온도에서 압반 전구체로서 사용된다. <ol><li> 적절한 도구를 사용하여 SiO2로 층의 두께, 예를 들어 반사 또는 엘 립소 미터를 확인한다. </li></ol></li><li> 코트 적절한 속도 (3500 RPM)에서 냉각 판, 스핀 코팅에 웨이퍼를 냉각 한 다음 130 ℃에서 90 초 HMDS 처리, 시작하여 포지티브 형 포토 레지스트의 1.4 μm의 가진 웨이퍼, 촉감 90 초 95 ℃에서 굽는다. </li><li> 포토 리소그래피 마스크 및 노광 툴을 사용하여, 나중에 그런가 2t 안으로 에칭 될 개구부의 원하는 패턴을, 노광O 정렬 마커에 정렬 비아를 형성하고, 노광량 140 mJ의 / cm 2. </li><li> 100 ℃에서 90 초간 현상 및 하드 베이크를 사용하여 60 초간 현상 한 다음 90 초 115 ° C의 노광 후 베이크로 시작하는 하나의 퍼들 현상 공정을 수행한다. </li><li> 레지스트의 개구부가 올바른 치수 및 정렬 마커에 오버레이가 올바른지 경우 검사 현미경을 사용합니다. </li><li> 플라즈마에 SiO2로 접촉 개구를 에칭. 예를 들어, C 2 F 6 단자 플라즈마 에칭을 사용 / CHF 3 1백44분의 36 SCCM 180 mTorr 내지 300 W의 RF 전력에서. 필요한 경우, 시간의 5 % -10 %의 오버 에칭 최소화하기 위해 테스트 웨이퍼에 대한 식각 율 테스트를 수행. 주 : TI는이 불소 화학 반응성 에칭에 저항하지만, 플라즈마에 장기간 노출 티 층의 물리적 에칭 발생합니다. TiN 층이 플라즈마에 노출되면이 부정적인 influen이있을 것이다CNT (12)의 성장에 CE. 이 구멍을 너무 많이 확대 될 것으로 제 4 부 문제에서 최고의 금속을, 습식 에칭을 사용하지 마십시오. </li><li> 60 초 동안 0.55 %의 HF 습식 에칭에 의해 희생 Ti 층을 제거합니다. 물 저항률까지 DI 물 린스 웨이퍼 에칭 후 5 MΩ이고 웨이퍼를 건조 린서 건조기를 사용한다. 주 : TI는 금속성 회색 인 반면, Ti 층을 에칭하는 경우는, 점검 할 수 현미경을 사용하여, TiN 층은 금 갈색을 가질 것이다. </li></ol> 3. 촉매 증착 및 탄소 나노 튜브 성장 <ol><li> 전자빔 증착기를 이용하여 5 nm의 공동을 증발시켰다. 적어도 2 × 10 -6 Torr로 펌핑 다운 될 때까지, 임의의 수막을 제거하기 위해 증착 전에 진공 하에서 램프를 사용하여 60 ° C로 웨이퍼를 가열한다. 포토 레지스트 접촉 개구를 정의하는 데 사용은 SiO2로에 접촉 개구에 촉매의 자기 정렬을 제공하기 위해 웨이퍼 상에 유지된다. </li><li> 풀다리프트 오프 (lift-off)에 의해 접촉 구멍 외부 공동. 공동 들어 그것은 테트라 하이드로 퓨란 (THF)이 낮은 온도에서 최적의 리프트 오프 결과와 성장을 제공 한 것으로 밝혀졌습니다. 이전 철 증발 후 리프트 오프 (lift-off)에 사용 된 N 개의 메틸 -2- 피 롤리 돈 (NMP)이, 손상 발견 공동 너무 정도로 모든 정렬 CNT의 성장을 방지 할 수있다. 35 ℃에서 THF와 초음파 조에서 15 분 동안 웨이퍼를 넣습니다. 5 분 동안 탈 이온수로 씻어 스피너 또는 질소 총을 사용하여 건조. </li><li> 현미경 아래에 웨이퍼를 검사하고 잔류 물에 저항을 확인합니다. 잔류 수동 잔류 물을 닦아 리프트 오프 (lift-off) 목적을위한 특별한 부드러운 면봉을 사용하여 선택적으로 THF에 이상 초음파 처리를 수행하고, 남아있는 경우. </li><li> 저압 화학 기상 증착 (LPCVD)을 이용하여 CNT의 성장을 수행한다. 50 SCCM의 C 2 H 2를 추가하여 탄소 나노 튜브 성장에 이어 80 밀리바에서 700 SCCM H 2로 350 ℃에서 8 분 전 어닐링 : 다음과 같은 조리법을 사용합니다. 350 ° C에서, (60)성장의 분은 약 1 μm의 탄소 나노 튜브의를 제공합니다. 필요하면 조정하는 시험을 성장의 SiO2 층과 동일한 두께이어야 높이를 수행한다. 원자로를 냉각 및 N 2를 사용하여 제거. </li><li> 또는 단면을 준비하여 45 ° 경사 아래 개구 내부 CNT의 높이를 검사하는 주사 전자 현미경을 사용한다. </li><li> CNT (18)의 결정 성을 결정하는 라만 분광법을 이용하여 시료를 검사한다. </li></ol> 4. 톱 사이드 금속 화 <ol><li> 최고 금속을 증착 마그네트론 스퍼터링을 사용합니다. TI는 CNT (19)와 접촉하기위한 양호한 금속이므로, 먼저 진공을 깨지 않고 알 (1 %의 Si) 2 ㎛의 Ti를이어서 100 nm의 스퍼터. </li><li> 코팅 3,000 rpm에서 콜드 플레이트, 스핀 코팅에 웨이퍼를 냉각 한 다음 130 ℃에서 90 초 HMDS 처리로 시작 높은 점도와 포지티브 형 포토 레지스트의 3.1 μm의, 및 90 초간 소프트 베이크시와 웨이퍼 (95)기음. </li><li> 포토 리소그래피 마스크 및 노광 툴을 사용하여 정렬 마커에 정렬 상부 금속 패턴, 노광량 420 mJ의 / cm 2, -1의 초점을 노출. </li><li> 하나의 웅덩이 개발 프로세스를 수행합니다. 이것은 100 ℃에서 개발자 90 초 하드 베이크를 사용하여 60 초 개발 한 다음, 90 초 115 ° C의 노출 후 베이킹을 시작합니다. </li><li> 레지스트의 라인이 올바른 치수 및 마커 오버레이가 올바른지 경우 검사 현미경을 사용합니다. </li><li> 염소 플라즈마 에칭을 이용하여 티타늄 / 알루미늄 스택을 에칭. 유도 결합 형 플라즈마를 사용하는 예를 들어 : 30/40 SCCM CL 2 / HBr을, 5 mTorr 이하, 종말점 검출하고, 80 %의 오버 에칭으로 압반 5백분의 40 W / ICP RF 전력은 15/30 SCCM CL 2 / HBr로를 사용. </li><li> 포토 레지스트 (1 킬로와트, 종말점 검출하고 2 분 과식 400 SCCM의 O 2)를 제거하기 위해 산소 플라즈마를 사용하여 스트리퍼. 금속 따르면이 완료되지 않은 경우 (즉, 핀홀 주위에 존재CNT)는 CNT에 플라즈마 손상을 방지하기 위해 포토 레지스트를 제거하기 위해, 유기 용매 (예를 들면, NMP)을 사용한다. </li><li> 웨이퍼를 청소합니다. 물의 비저항은 5 MΩ (유기 청소) 될 때까지 탈 이온수로 세척 한 다음 99 % HNO 3, 10 분 동안 넣어. 웨이퍼를 건조 린서 드라이어를 사용합니다. </li></ol> 5. 측정 <ol><li> 웨이퍼의 상부 금속 화를 확인하기 위해 제조업 자의 지시에 따라 주 사형 전자 현미경을 사용한다. 주 :.도 3에 도시 된 바와 같이, 웨이퍼는 기계적 이미지 결과 90 ° 샘플 기울기를 사용을 통해 완전한 CNT를 확인하기 위해서 절단 될 수있는 필요하다면 시료를 도전대로 추가적인 처리 단계를 사용하지 않는 것으로하고 샘플은 직접 SEM에 장착 될 수있다. 일반적으로, 15 또는 20 kV의 높은 가속 전압이 사용될 수 있지만, 경우의 SiO2 층이 너무 많이 감소시킬 수 t를 충전되고5 kV의를 오. </li><li> 4- 포인트를 수행하고도 1에 Vollebregt 외. (16)에 기재된 반도체 파라미터 분석기와 결합 프로브 스테이션을 사용하여 프로브 IV 측정. 참고 : 상호 연결을 통해 잠재적 인 드롭이 이상적으로 작은로서 일반적으로 -0.5 V 0.5에서 전압 스윕은 충분하다. 4- 포인트 프로브 설정을 이용하여 프로브 침과 설치의 와이어 저항의 접촉 저항을 생략한다. </li></ol>

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H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Electrical+Improvement+of+CNT+Contacts+with+Cu+Damascene+Top+Metallization.">Electrical Improvement of CNT Contacts with Cu Damascene Top Metallization.</a> Proceedings of the IEEE International Interconnect Technology Conference. , 193-195 (2013).</li><li>Istratov, A. A., Hieslmair, H., Weber, E. R. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Iron+contamination+in+silicon+technology.">Iron contamination in silicon technology.</a> Appl. Phys. A. 70, 489-534 (2000).</li><li>Vollebregt, S., Tichelaar, F. D., Schellevis, H., Beenakker, C. I. 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M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Influence+of+the+growth+temperature+on+the+first+and+second-order+Raman+band+ratios+and+widths+of+carbon+nanotubes+and+fibers.">Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers.</a> Carbon. 50 (10), 3542-3554 (2012).</li><li>Lim, S. C., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Contact+resistance+between+metal+and+carbon+nanotube+interconnects:+Effect+of+work+function+and+wettability.">Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability.</a> Appl. Phys. Lett. 95 (26), 264103 (2009).</li><li>Awano, Y., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Carbon+nanotube+via+interconnect+technologies:+size-classified+catalyst+nanoparticles+and+low-resistance+ohmic+contact+formation.">Carbon nanotube via interconnect technologies: size-classified catalyst nanoparticles and low-resistance ohmic contact formation.</a> Phys. Status Solidi (a). 203 (14), 3611-3616 (2006).</li><li>Van der Veen, M. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Electrical+characterization+of+CNT+contacts+with+Cu+Damascene+top+contact.">Electrical characterization of CNT contacts with Cu Damascene top contact.</a> Microelectron. Eng. 106, 106-111 (2012).</li><li>Horibe, M., Nihei, M., Kondo, D., Kawabata, A., Awano, Y. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Mechanical+Polishing+Technique+for+Carbon+Nanotube+Interconnects+in+ULSIs.">Mechanical Polishing Technique for Carbon Nanotube Interconnects in ULSIs.</a> Jpn J. App. Phys. 43 (9A), 6499-6502 (2004).</li><li>Vollebregt, S., Chiaramonti, A. N., Ishihara, R., Schellevis, H., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Contact+resistance+of+low-temperature+carbon+nanotube+vertical+interconnects.">Contact resistance of low-temperature carbon nanotube vertical interconnects.</a> Proceedings of the 12th IEEE Conference on Nanotechnology. , 424-428 (2012).</li><li>Fiorentino, G., Vollebregt, S., Tichelaar, F. D., Ishihara, R., Sarro, P. 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The authors have nothing to disclose.

도 1은 본 연구에서 제작 한 구조물의 개략도를 표시하고, 이는 4 점 탐침 측정에 사용 하였다. 전위가 전류를 운반하지 프로브에 의해 측정 된 바와 같이, 중앙 CNT 다발과 금속과의 접촉을 통해 정확한 전위 강하 (V H 종의 -V L)를 측정 할 수있다. 더 큰 직경의 CNT 번들 강제 전류 프로브의 전체 저항을 감소시키고 중앙 CNT 다발 위에 전위 강하를 최대화하기 위해, 접촉 ?...

구리, 텅스텐, 현재 최첨단 매우-대규모 통합 (VLSI) 기술의 상호 연결에 사용되는 금속은 안정성과 전기 전도성 1의 관점에서 물리적 한계에 접근하고있다. 다운 스케일링 트랜지스터는 일반적으로 그들의 성능이 향상되지만, 실제로 저항 및 배선의 전류 밀도를 증가시킨다. 이것은 지연 및 전력 소비의 측면에서 2 집적 회로 (IC)의 성능을 지배 상호 결과. 탄소 나노 튜브 (CNT)는 수직 상호 탄소 나노 튜브로 (비아) 쉽게 3 수직 성장하고 있습니다 특히 위해, Cu 및 W 금속에 대한 대안으로 제안되었다. CNT는 Cu를 4보다 1000 배 더 높은 전류 밀도를 최대 허용 우수한 전기적 안정성을 보여왔다. 또한, CNT가 표면 및 입자 경계 산란 겪지 않으며, 이는 R을 증가나노 미터 스케일 (5)에서 구리의 esistivity. 마지막으로, CNT는 VLSI 칩의 열 관리에 도움이 될 수있다 우수한 열 전도체 (6) 인 것으로 밝혀졌다. VLSI 기술에 대한 CNT의 성공적인 통합 것이 대한 CNT 성장 프로세스가 반도체 제조 양립하는 것이 중요하다. 이는 물질 및 대규모 제조에 호환 및 확장 장치를 고려하여 CNT (&lt;400 °의 C)의 저온 성장을 필요로한다. CNT 시험 비아의 많은 예들은 7,8,9,10,11,12,13,14 문헌에서 설명되었지만, 이들의 대부분은 오염 물질의 IC (15)를 제조하는 것으로 간주되는 철을 촉매로 사용한다. 게다가, 이러한 많은 작품에서 사용되는 성장 온도가 400 ° C의 상한보다 훨씬 높다. 바람직 CNT도 현대 저 κ 유전체 또는가요 성 통합을 허용하기 위해, 350 ° C 이하로 성장되어야기판. 여기에서 우리는 촉매 (16)로 공동을 사용하여 350 ℃의 낮은 온도에서 탄소 나노 튜브를 성장을위한 확장 가능한 방법을 제시한다. 이 방법은, 집적 회로에서 수직 배향 CNT 이루어진 다른 전기적 구조들을 제조하는 수퍼 커패시터 및 전계 방출 소자로 상호 연결 전극 이르기위한 관심사이다. 주석은 종종 사용 차단재 7 동안 공동 촉매 금속은 종종 실리사이드의 (17)의 제조를 위해 IC 제조에서 사용된다. 더욱이, 우리는 표준 반도체 제조 기술에서 사용 중에 CNT 시험 비아를 제조하기위한 프로세스를 보여준다. 이에 의해, CNT 시험 비아 전자 현미경 (SEM) 및 라만 분광법, 전기적 특성화를 스캔하여 검사, 제조된다.

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

이 연구에서 사용 된 측정 구조의 설계는도 1에서 발견 될 수있다. 탐침 및 와이어 저항을 회피 한, CNT 다발 저항과 금속 CNT의 접촉 저항의 측정이 정확하게 판정 될 수있는 구조를 채용함으로써. 다발의 저항은 CNT 다발의 품질과 밀도를 측정한다. 상이한 길이의 접촉 저항 번들을 결정하기 위하여 측정한다. 45 ° 기울기에서 금속 화 전에 위쪽에서 찍은 60 분 동안...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

반도체 기술과 호환 저온 탄소 나노 튜브 수직 상호 연결의 제작

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Research

JoVE Journal

Engineering

7.6K 조회수.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

비디오: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

3D 카본 나노튜브 Microstructures의 제조, Densification 및 복제 성형

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

연구

공학

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

Nanoskiving으로 Nanogaps을 제조

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

화학

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

탄소 나노 튜브 배열의 으러 속성을 조정을위한 트리트먼트 소둔 건식 산화, 진공

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

임의 기판에 수직으로 정렬 작은 분자 유기 나노 와이어의 초 밀도 배열

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

미세 유체 침투를 통해 세 가지 차원 미세 구조 나노 복합 재료의 제조

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

실리콘 다이렉트 웨이퍼 본딩을 통한 균일한 나노스케일 캐비티 제조

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

높은 이온 강도 솔루션에 감지하기위한 탄소 나노 튜브 고주파 나노 바이오 센서의 제작

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

생체공학

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

흐름 기반 Dielectrophoresis: 고성능 솔루션 처리 나노와이어 소자의 제조에 대 한 낮은 비용 방법

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

2 차원 일렉트로닉스를 조작 하는 표준 및 신뢰할 수 있는 방법

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.