Name: fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology
Uploaded: 2015-12-07T13:00:00.000+00:00
Duration: 9 min 20 s
Description: Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Caution: Please consult all relevant material safety data sheets (MSDS) before use. Several of the chemicals used in this fabrication process are acutely toxic and carcinogenic. Nanomaterials may have additional hazards compared to their bulk counterpart. Please use all appropriate safety practices when working with equipment, chemicals or nanomaterials, including the use of engineering controls (fume hood) and personal protective equipment (safety glasses, gloves, cleanroom clothes).
1. Alignment Marker Definition for Lithography
<ol>
	<li>Start with single-sided polished industrial grade Si(100) wafers with either n or p-type doping.</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist. Perform a 90 sec hexamethyldisilazane (HMDS) treatment at 130 &#176;C to promote adhesion of the photoresist, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the alignment markers, exposure dose 120 mJ/cm2.</li>
	<li>Perform a single puddle development process. Perform a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C to cure the resist.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions.</li>
	<li>Etch 120 nm of Si using chlorine plasma etching. This thickness gives good contrast for the automatic alignment systems of the exposure tool used in this work. For example using an inductive coupled plasma (ICP): 20/40 sccm O2/CF4, 5 mTorr, 60/500 W platen/ICP RF power, 10 sec oxide breakthrough etching, followed by 80/40 sccm Cl2/HBr, 60 mTorr, 20/500 W platen/ICP RF power, 35 sec Si etch.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). As the photoresist is cured by the plasma normal solvent like acetone cannot be used.</li>
	<li>Clean the wafers. First put them for 10 min in 99% HNO3, followed by rinsing in DI water till the resistivity of the water is 5 M&#937; (organic clean). After this clean the wafers for 10 min in 65% HNO3 at 110 &#176;C, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (metal clean). Use a rinser dryer to dry the wafers.</li>
</ol>
2. Bottom Metal and Interlayer Dielectric Deposition
<ol>
	<li>Use magnetron sputtering to deposit the bottom metal layer of the test via. A stack of three metal layers needs to be deposited: 500 nm of Ti, 50 nm of TiN, and 100 nm Ti. The first Ti layer is to reduce the resistance of the stack, the TiN is the actual support layer for CNT growth, and the top Ti is to protect the TiN against plasma damage when etching the SiO2 layer12. Perform Ti sputtering using a pure Ti target with Ar-plasma at a substrate temperature of 350 &#176;C. For TiN reactive sputtering use a combination of Ar and N2, again at 350 &#176;C substrate temperature.</li>
	<li>Using plasma-enhanced chemical vapor deposition (PECVD), deposit a 1 &#181;m thick layer of SiO2. Here tetraethyl orthosilicate (TEOS) is used as precursor at a platen temperature of 350 &#176;C.
	<ol>
		<li>Check the thickness of the SiO2 layer using an appropriate tool, for instance a reflectometer or ellipsometer.</li>
	</ol>
	</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool, expose the desired pattern of openings, which will be later etched into the SiO2 to form the vias, aligned to the alignment markers, exposure dose 140 mJ/cm2.</li>
	<li>Perform a single puddle development process starting with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions and if the overlay to the alignment markers is correct.</li>
	<li>Plasma etch the contact openings in the SiO2. For example, use a triode plasma etcher with C2F6/CHF3 36/144 sccm at 180 mTorr and 300 W RF power. If necessary, perform etch rate tests on a test wafer in order to minimize over etching to 5%-10% in time. 
	Note: Although the Ti is resistant to reactive etching in this fluorine chemistry, prolonged exposure to the plasma will result in physical etching of the Ti layer. If the TiN layer is exposed to the plasma this will have a negative influence on the growth of the CNT12. Do not use wet etching as this will result in too much widening of the openings, making the top metallization in part 4 problematic.</li>
	<li>Remove the sacrificial Ti layer by wet etching in 0.55% HF for 60 sec. After etching rinse the wafers with DI water till the water resistivity is 5 M&#937; and use a rinser dryer to dry the wafers. 
	Note: Using a microscope it can be checked if the Ti layer is etched, the TiN layer will have a gold-brown color while the Ti is metallic grey.</li>
</ol>
3. Catalyst Deposition and CNT Growth
<ol>
	<li>Evaporate 5 nm of Co using an e-beam evaporator. Pump down till at least 2x10-6 Torr, and heat the wafers to 60 &#176;C using lamps under vacuum before depositing to remove any water film. The photo-resist used to define the contact openings is kept on the wafer to provide self-alignment of the catalyst to the contact openings in the SiO2.</li>
	<li>Remove the Co outside the contact openings by lift-off. For Co it was found that tetrahydrofuran (THF) gives the best lift-off results and growth at low temperatures. N-methyl-2-pyrrolidone (NMP), which was previously used for lift-off after Fe evaporation, was found to damage the Co too such an extent to prevent any aligned CNT growth. Put the wafer for 15 min in an ultrasonic bath with THF at 35 &#176;C. Rinse with DI water for 5 min and dry using a spinner or nitrogen gun.</li>
	<li>Inspect the wafer underneath a microscope and check for resist residues. If residues remain perform a longer ultrasonic treatment in THF, and optionally use a special soft cotton swab for lift-off purposes to manually wipe away residues.</li>
	<li>Perform CNT growth using low-pressure chemical vapor deposition (LPCVD). Use the following recipe: 8 min pre-anneal at 350 &#176;C with 700 sccm H2 at 80 mbar, followed by CNT growth by adding 50 sccm C2H2. At 350 &#176;C, 60 min of growth gives roughly 1 &#181;m of CNT. If necessary perform a test growth to tune the height, which should be the same thickness as the SiO2 layer. Cool down the reactor and purge using N2.</li>
	<li>Use a scanning electron microscope to check the height of the CNT inside the openings under 45&#176; tilt, or by preparing a cross-section.</li>
	<li>Inspect the samples using Raman spectroscopy to determine the crystallinity of the CNT18.</li>
</ol>
4. Topside Metallization
<ol>
	<li>Use magnetron sputtering to deposit the top metal. As Ti is a good metal for contacting CNT19, first sputter 100 nm of Ti, followed by 2 &#181;m of Al (1% Si) without breaking the vacuum.</li>
	<li>Coat the wafer with 3.1 &#181;m of positive photoresist with higher viscosity, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at 3,000 rpm, and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the top metal pattern aligned to the alignment markers, exposure dose 420 mJ/cm2, focus of -1.</li>
	<li>Perform a single puddle development process. This starts with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the lines in the resist are of the correct dimensions and if the overlay to the markers is correct.</li>
	<li>Etch the Ti/Al stack using chlorine plasma etching. For example using an inductive coupled plasma: 30/40 sccm Cl2/HBr, 5 mTorr, 40/500 W Platen/ICP RF power with endpoint detection and 80% overetch using 15/30 sccm Cl2/HBr.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). If the metal coverage is not complete (i.e., there are pinholes around the CNT) use an organic solvent (e.g., NMP) to remove the photoresist in order to prevent plasma damage to the CNT.</li>
	<li>Clean the wafers. Put them for 10 min in 99% HNO3, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (organic clean). Use a rinser dryer to dry the wafers.</li>
</ol>
5. Measurements
<ol>
	<li>Use a scanning electron microscope according to manufacturer&#39;s instructions to check the top metallization of the wafers. 
	Note: If necessary the wafer can be mechanically cleaved in order to check the complete CNT via using a sample tilt of 90&#176;, resulting in images as shown in Figure 3. As the samples are electrically conductive no additional treatment steps have to be used and the samples can be directly mounted into the SEM. Generally, high acceleration voltages of 15 or 20 kV can be used, but if the SiO2 layer is charging up too much this can be reduced to 5 kV.</li>
	<li>Perform 4-point probe I-V measurements using a probe station in combination with a semiconductor parameter analyzer as described in Figure 1 and in Vollebregt et al. 16. 
	Note: Normally a voltage sweep from -0.5 to 0.5 V is sufficient, as the potential drop over an interconnect ideally is small. By using a 4-point probe setup the contact resistance of the probe needles and the wire resistances of the setup are omitted.</li>
</ol>

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The authors have nothing to disclose.

Figure 1 displays a schematic overview of the structure fabricated in this work, and which was used for the 4-point probe measurements. As the potential is measured through probes carrying no current, the exact potential drop (VH-VL) over the central CNT bundle and its contacts to the metal can be measured. Bigger diameter CNT bundles are used to contact the bottom TiN layer from the contact pads, in order to reduce the total resistance for the current forcing probes and maximize the potential drop over the central CNT bundle.
As can be seen from Figure 2, the CNT were successfully grown inside the openings etched in the SiO2 with a length approximately the same as the depth of the hole (1 &#181;m). It is crucial that the length of the CNT is roughly the same as the depth of the hole, in order to achieve conformal coating of the top metal contact. The bundles appear uniform, which also aids in conformal coating of the metal. The straightness and vertical alignment of the tubes can clearly be seen in the cross-section displayed in Figure 3. By counting, the density of the CNT bundle was estimated to be around 5x1010 tubes/cm2. Using transmission electron microscopy the average diameter of the tubes was found to be 8 nm, as was shown elsewhere16. Due to the low growth temperatures the CNT walls contain many defects making determining the number of walls difficult. The tubes appear to have a hollow core, although bamboo crossings have been observed. The cross-section also shows the bottom TiN layer, and the sacrificial Ti layer which is partly removed underneath the SiO2 during the wet etching. If openings are placed closed together the etching time of the sacrificial Ti layer may have to be optimized to minimize underetch to prevent oxide delamination. Due to the dry etching of the hole, the spacing between the SiO2 and CNT bundle is minimal, which is essential to prevent the sputtered Ti and Al from forming short circuits around the CNT bundle.
Using the Raman data the crystallinity (or quality) of the CNT can be investigated. As the different Raman bands are close to each-other deconvolution of the bands is necessary, as described elsewhere18. From the Raman data in Figure 4 it is apparent that a strong D and D&#8217; band can be observed, which are caused by Raman scattering with defects, while the G band is related to the C-C bond. The other two bands are weak Raman features which are included for more accurate fitting.
It is known that a low growth temperature in general results in a lower CNT quality18. Usually the D over G intensity ratio (ID/G) is used to assess the quality of graphitic materials, which is 1.1 in Figure 4. As has been shown by for instance Ferrari and Robertson20, care has to be taken when using only this band ratio. With increasing quality of the CNT, first the ID/G ratio increases, till a certain amount of crystallization is reached after which the ratio decreases monotonically. Due to the very low growth temperature, the CNT in this work appear to have a crystallinity below this threshold16. In these cases the full-width at half maximum of the D band can be used to compare CNT samples fabricated at different process conditions18. It can be expected that the low quality of the CNT will significantly influence the electrical performance.
Judging from the almost complete linear behavior of the I-V characteristics in Figure 5, the contacts between the CNT and the top and bottom metal layers are ohmic. The resistance of the bundle decreases with diameter, which is to be expected as more CNT can conduct in parallel for larger bundles. The good contact between the CNT and the metals is attributed to the use of Ti19, and TiN which is more resilient against oxidation21. Besides, we found that due to the lack of any dielectric covering steps of the CNT after growth (using for instance spin-on glass), something which is often used in the literature in combination with chemical mechanical polishing (CMP)22,23, the contact resistance to the CNT is low due to embedding of the CNT tips in the top metal24.
When comparing the resistivities of the CNT bundles with literature, as is done in Figure 6, the results are among the average values in the literature. However, the growth temperature used in this work is record-low. The results of Yokoyama et al. 13 are the lowest resistivity reported in the literature, using only a 40 &#176;C higher growth temperature. However, the equipment used for Co particle deposition in their work is likely not scalable to large volume manufacturing. Clearly the resistivity decreases with increasing growth temperature, which can be advantageous for application allowing higher growth temperatures. When comparing the resistivity of the CNT bundles with traditional interconnect metals like Cu (1.7 &#181;&#937;-cm), it is apparent that a drastic reduction of the resistivity is required. Improving the quality of the CNT and the bundle density, by optimizing the growth conditions, will be required. This has to be done without increasing the growth temperature, in order to allow integration with modern low-&#954; materials and flexible substrates.
We have thus demonstrated a technique for integrating low temperature CNT growth and integration into standard semiconductor fabrication. This technique has been used to fabricate CNT via test structures and has recently been applied for the fabrication of CNT super capacitors25.

Copper and tungsten, the metals which are currently used for the interconnects in state-of-the-art very-large-scale integration (VLSI) technology, are approaching their physical limits in terms of reliability and electrical conductivity1. While down-scaling transistors generally improves their performance, it actually increases the resistance and current density of the interconnects. This resulted in interconnects dominating the integrated circuit (IC) performance in terms of delay and power consumption2.
Carbon nanotubes (CNT) have been suggested as alternative for Cu and W metallization, especially for vertical interconnects (vias) as CNT can easily been grown vertical3. CNT have been shown to have excellent electrical reliability, allowing an up to 1,000 times higher current density than Cu4. Moreover, CNT do not suffer from surface and grain boundary scattering, which is increasing the resistivity of Cu at the nanometer scale5. Finally, CNT have been shown to be excellent thermal conductors6, which can aid in the thermal management in VLSI chips.
For successful integration of CNT in VLSI technology it is important that the growth processes for the CNT is made compatible with semiconductor fabrication. This requires the low temperature growth of CNT (&#60; 400 &#176;C) using materials and equipment which are considered compatible and scalable to large scale manufacturing. While many examples of CNT test vias have been demonstrated in the literature7,8,9,10,11,12,13,14, most of these use Fe as catalyst which is regarded as a contaminant in IC manufacturing15. Besides, the growth temperature used in many of these works is much higher than the upper limit of 400 &#176;C. Preferably CNT should even be grown below 350 &#176;C, in order to allow integration with modern low-&#954; dielectrics or flexible substrates.
Here we present a scalable method for growing CNT at temperatures as low as 350 &#176;C using Co as catalyst16. This method is of interest for fabricating different electrical structures consisting of vertically aligned CNT in integrated circuits, ranging from interconnect and electrodes to super capacitors and field emission devices. The Co catalyst metal is often used in IC manufacturing for the fabrication of silicide&#8217;s17, while TiN is an often used barrier material7. Moreover, we demonstrate a process for fabricating CNT test vias while only using techniques from standard semiconductor manufacturing. With this, CNT test vias are fabricated, inspected by scanning electron microscopy (SEM) and Raman spectroscopy, and electrically characterized.

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

The design of the measurement structure used in this work can be found in Figure 1. By employing such a structure the measurement of the CNT bundle resistance and the metal-CNT contact resistances can be determined accurately, as probe and wire resistances are circumvented. The resistance of the bundle is a measure for the quality and density of the CNT bundle. In order to determine the contact resistance bundles of different lengths should be measured.
A typical SEM image of CNT grown at 350 &#176;C for 60 min taken from the top before metallization at 45&#176; tilt is shown in Figure 2. Such an image is useful for checking if the growth time of the CNT is correctly set in order to obtain the same length as the thickness of the SiO2 layer. A cross-section prepared by mechanical cleaving inspected by SEM of the same wafer after metallization is shown in Figure 3. This can be used to determine the alignment of the CNT, their density (for instance be counting the number of CNT per unit length), and if a high resolution SEM is used to determine their diameter. Also the contact area between the CNT and the metal layers can be investigated.
Raman spectra of Co-grown CNT at 350 &#176;C is displayed in Figure 4. Raman spectroscopy is a powerful technique for investigating the crystallinity of the CNT18, and can for instance be used to optimize the CNT growth parameters in order to obtain the highest quality CNT. I-V measurements were performed using four point probe structures and are displayed in Figure 5. When the I-V behavior is linear it indicates ohmic contact between the CNT and the metal contacts. From the slope the electric resistance can be determined. From the resistance and the dimension of the bundles the resistivity can be calculated, which for these CNT bundles is compared to the literature in Figure 6.
<img alt="Figure 1" src="/files/ftp_upload/53260/53260fig1.jpg" /> 
Figure 1. Design of 4-point probe measurement structure used in this work. In the figure the dark yellow layer indicates the TiN, the black tubes the CNT bundles, and the metallic layer the Ti and Al stack. The sacrificial Ti layer is omitted for clarity and the oxide is semi-transparent. Probe connections for electrical 4-point probe measurements are indicated. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig1large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 2" src="/files/ftp_upload/53260/53260fig2.jpg" /> 
Figure 2. Top-view SEM image of a CNT bundle. This shows a 2 &#181;m wide CNT bundle grown in a contact opening which was etched inside the SiO2. This figure has been modified from 16, with permission from Elsevier. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig2large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 3" src="/files/ftp_upload/53260/53260fig3.jpg" /> 
Figure 3. SEM cross-section of CNT via. Cross-section of a 2 &#181;m wide and 1 &#181;m long CNT test via prepared using mechanical cleaving after metallization. This figure has been modified from 16, with permission from Elsevier. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig3large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 4" src="/files/ftp_upload/53260/53260fig4.jpg" /> 
Figure 4. Raman spectrum of a CNT bundle grown using Co at 350 &#176;C. The names of the Raman bands are indicated. The black curve displays the raw measurement data. For all bands a Lorentzian fitting is performed (green dashed curves), except for the D&#8217; band which is fitted by a Gaussian18. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig4large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 5" src="/files/ftp_upload/53260/53260fig5.jpg" /> 
Figure 5. I-V measurements of CNT test vias with different diameters. The symbols represent the measurement data, while the solid line indicates a linear least squares fitting to the measurement data. The electrical resistances of the different vias as determined from the slope of the linear fitting are indicated. This figure has been modified from 16, with permission from Elsevier. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig5large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 6" src="/files/ftp_upload/53260/53260fig6.jpg" /> 
Figure 6. Comparison of CNT bundle resistivity with values from the literature. The resistivity is calculated from the resistance and the via dimensions. It is compared with values from the literature, and CNT vias fabricated at different temperatures using the method described in this work. This figure has been modified from 16, with permission from Elsevier. <a href="https://www.jove.com/files/ftp_upload/53260/53260fig6large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Nanyang Technological University

Research

JoVE Journal

Engineering

7.6K Views.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Video: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Chemistry

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengineering

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.