We thank K. Y. Tan, P. See and G. C. Tettamanzi for useful discussions. We acknowledge financial support from the Australian Research Council (Grant No. DP120104710), the Academy of Finland (Grant No. 251748, 135794, 272806) and support from the Australian National Fabrication Facility for device fabrication. A.R. acknowledges financial support from the University of New South Wales Early Career Researcher Grant scheme. The provision of facilities and technical support by Aalto University at Micronova Nanofabrication Centre is also acknowledged.

Note: This protocol describes the procedures used to fabricate, package and test single-electron pumps based on silicon MOS QD technology. The steps discussed in sub-sections 1 and 2 are carried out in an ISO5 cleanroom, while those of section 3 are performed in ISO6 laboratories. Ambient conditions are continuously controlled. Nominal values for temperature and humidity are set at 20 &#177; 1 &#176;C and 55% &#177; 5%, respectively.
1. Microfabrication
<ol>
	<li>Field Oxide
	<ol>
		<li>Clean the wafer by immersion in the following: piranha etch (10 min), deionized (DI) water (10 min), RCA-2 solution (DI water 175 ml, HCl 30 ml, H2O2 30 ml at 100 &#176;C for 10 min), deionized water (5 min), hydrofluoric (HF) acid diluted in water 10:1 (10 sec), DI water (10 min). Use protective garments when handling HF (i.e., goggles, PVC apron, and PVC gloves). Proceed in the stated order.</li>
		<li>Place the wafer in oxidation furnace at 900 &#176;C and oxidize in steps as follows: dry O2 (10 min), wet O2 (40 min), dry O2 (10 min), N2 (15 min).</li>
	</ol>
	</li>
	<li>Ohmic Contacts
	<ol>
		<li>Carry out photolithography and etch oxide.
		<ol>
			<li>Deposit a few-nm-thick layer of adhesion promoter hexamethyldisilazane (HMDS) onto the wafer surface as follows: pre-bake on a hotplate at 110 &#176;C for 1 min, pour ~50 ml of HMDS in a glass beaker, place the beaker and the wafer in the vacuum chamber, evacuate and wait for 2 min.</li>
			<li>Spin a 2&#8211;4-&#956;m-thick layer of photoresist on both back and front sides of the wafer (3,000&#8211;5,000 rpm, 25&#8211;40 sec depending on desired thickness).</li>
			<li>Expose to ultra-violet light in mask aligner (10 mW/cm2 for 4&#8211;10 sec according to resist thickness). Post-bake on a hotplate at 110 &#176;C for 1 min.</li>
			<li>Develop for 1&#8211;2 min, then rinse in deionized water.</li>
			<li>Perform O2 plasma etch for 20 min (pressure = 340 mTorr; incident power = 50 W; reflected power &#60; 1 W).</li>
			<li>Etch oxide in buffered HF acid solution (15:1, 4&#8211;5 min, etch rate &#8776; 20 nm/min at 30 &#176;C). Rinse in deionized water (5 min). Blow dry with N2.</li>
		</ol>
		</li>
		<li>Remove photoresist by immersion in acetone. Rinse in isopropanol (IPA), then blow dry with N2.</li>
		<li>Place wafer in furnace at 1,000 &#176;C with phosphorus source (N2 flow for 30&#8211;45 min depending on desired doping density).</li>
		<li>Remove contaminated oxide layer with HF acid diluted in water (10:1, 3&#8211;4 min, etch rate &#8776; 40 nm/min at 30 &#176;C), rinse in deionized water (10 min).</li>
		<li>Oxidize as in 1.1.2.</li>
	</ol>
	</li>
	<li>Gate Oxide
	<ol>
		<li>Repeat steps 1.2.1 and 1.2.2.</li>
		<li>Place wafer in dedicated furnace at 800 &#176;C and oxidize in steps as follows: dry O2 (10 min), dichloroethylene+O2 (20 min), dry O2 (10&#8211;30 min depending on desired oxide thickness), N2 (15 min).</li>
	</ol>
	</li>
	<li>Ohmic Contacts Metallization
	<ol>
		<li>Repeat step 1.2.1.</li>
		<li>Place wafer in electron-beam evaporator. Evaporate 100 nm of aluminum at 0.2&#8211;0.5 nm/sec and 5 x 10-6 Torr.</li>
		<li>Soak the wafer in N-methyl-2-pyrrolidone (NMP) on hotplate at 80 &#176;C for 1 hr to lift off the metal. Use ultrasonic agitation if needed. Rinse in IPA for 2 min. Blow dry with N2.</li>
		<li>Anneal in forming gas at 400 &#176;C for at least 15 min.</li>
	</ol>
	</li>
</ol>
2. Nanofabrication
<ol>
	<li>Wafer Dicing
	<ol>
		<li>Spin any resist onto the wafer to act as protective coating (type of polymer and spinning parameters are irrelevant at this stage).</li>
		<li>Use diamond tip dicer to cut the wafer into individual chips of ~10 x 2 mm2.</li>
	</ol>
	</li>
	<li>Cleaning
	<ol>
		<li>Soak in NMP for 1 hr on hotplate at 80 &#176;C, then rinse in IPA for 2 min. Blow dry with N2.</li>
		<li>Perform O2 plasma etch for 5 min (incident power = 50 W; reflected power &#60; 1 W).</li>
		<li>Spin clean with acetone and IPA (7,500 rpm, 30 sec)</li>
	</ol>
	</li>
	<li>Alignment markers patterning
	<ol>
		<li>Spin polymethyl methacrylate (PMMA 950k) A4 resist (5,000&#8211;7,500 rpm, 30 sec depending on desired thickness). Typical working thickness &#8776; 150&#8211;200 nm. Bake the resist on a hotplate at 180 &#176;C for 90 sec.</li>
		<li>Carry out e-beam lithography. Use the following write conditions: beam energy = 30 keV, beam current &#8776; 30 pA, area dose &#8776; 500&#8211;650 &#181;C/cm2 depending on markers size and resist thickness.</li>
		<li>Develop the resist in a solution of methyl isobutyl ketone and IPA (1:3) for 40&#8211;60 sec, then rinse in IPA for 20 sec. Blow dry with N2 gun.</li>
		<li>Place the chip in electron-beam evaporator. Evaporate 15 nm of Ti and 65 nm of Pt at 0.2&#8211;0.4 nm/sec and 5 x 10-6 Torr.</li>
		<li>Lift off the metal as in step 1.4.3.</li>
		<li>Clean chip as in steps 2.2.2&#8211;2.2.3.</li>
	</ol>
	</li>
	<li>Gate patterning
	<ol>
		<li>Spin resist as in 2.3.1.</li>
		<li>Carry out e-beam lithography. Use the following write conditions for high resolution features: beam energy = 30 keV, beam current &#8776; 30 pA, area dose &#8776; 500&#8211;700 &#181;C/cm2. Write conditions for low resolution features: beam energy = 15 keV, beam current &#8776; 10 nA, area dose &#8776; 400&#8211;600 &#181;C/cm2.</li>
		<li>Develop the resist as in 2.3.3.</li>
		<li>Place the chip in thermal evaporator. Evaporate Al at 0.1&#8211;0.4 nm/sec and 1&#8211;9 x 10-6 mbar. Target thickness varies according to layer number, as shown in Figure 2B (25&#8211;35 nm for Layer 1, 45&#8211;65 nm for Layer 2, 75&#8211;90 nm for Layer 3).</li>
		<li>Lift off the metal as in step 1.4.3.</li>
		<li>Perform Al oxidation on a hotplate at 150 &#176;C for 5&#8211;10 min.</li>
		<li>Clean chip as in step 2.2.3.</li>
		<li>Repeat steps 2.4.1&#8211;2.4.7 twice to realize the 3-layer gate stack.</li>
	</ol>
	</li>
</ol>
3. Device Packaging
<ol>
	<li>Dice chip as in step 2.1</li>
	<li>Rinse the resulting smaller chips in acetone and IPA for 2 min.</li>
	<li>Glue an individual piece to a printed circuit board (PCB) with PMMA A5. Wait 2 min for it to dry. Alternatively, to enhance thermalization, use silver epoxy.</li>
	<li>Load the PCB onto a wedge bonder and proceed with wiring.</li>
</ol>
4. Device Integrity Tests
<ol>
	<li>Mount the PCB containing the wired device onto a dip probe.</li>
	<li>Wire the electrical lines of the PCB to those of the dip probe.</li>
	<li>Insert the probe into a vessel containing liquid helium. Proceed slowly to avoid excessive helium boil-off.</li>
	<li>For each device gate, connect the corresponding room-temperature electrode of the probe to a source-measure unit, while keeping the other gates grounded. Set the compliance current to few nA. Sweep the voltage from zero to 1.5V in steps of 0.1 V, measure and record the current.</li>
	<li>Connect each gate line to a battery-powered variable dc voltage source, the source line to the built-in ac voltage source of a lock-in amplifier, and the drain line to the input port of the lock-in amplifier.</li>
	<li>Measure the source to drain conductance for different gate voltage configurations (see Figure 4).
	<ol>
		<li>Globally ramp up the voltages applied to gates BL, BR, PL, SL and DL, by keeping C1 and C2 gates grounded. Record the &#8216;turn-on&#8217; device characteristics.</li>
		<li>Individually ramp down each gate voltage and record the gates &#8216;pinch-off&#8217; characteristics.</li>
		<li>Adjust the gate voltages to electrostatically define a quantum dot by setting the voltages on BL and BR (PL, SL and DL) smaller (greater) than the turn-on voltages. Record the Coulomb blockade characteristics.</li>
	</ol>
	</li>
</ol>

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The authors have nothing to disclose.

The protocol reported in this paper describes the techniques to fabricate silicon MOS QDs, as well as the experimental procedures to test their functional integrity and operate them as single-electron pumps. Remarkably, by tailoring the gate design, the same fabrication process can be employed to produce devices suitable for quantum bit readout and control17, as well as charge pumping12,13. We note that many of the process parameters quoted in this article may vary depending on the fabrication tools used (calibration, make or model), as well as on the type of silicon substrate (thickness and background doping density). Quantities such as lithography exposure dose or development time, etching or oxidation duration, have to be carefully calibrated and tested to ensure a reliable yield. Furthermore, it is crucial to avoid cross-contamination arising from the use of the same fabrication tools for different processes. To this end, a number of critical steps are carried out with equipment exclusively dedicated to silicon processing such as metal evaporators, oxygen furnaces and HF baths.
More generally, silicon is drawing a growing interest as the material of choice to realize charge pumps18-20. This is partly due to the attractive perspective of implementing a new quantum-based electric current standard using an industry-compatible silicon process. This would benefit from well-established and reliable integration techniques for scalability, parallelization and driving overhead. Importantly, a full complementary MOS (CMOS) technology, free of traditional metal as the gate material, has shown greatly reduced background charge fluctuations in single-electron devices21. Such fluctuations can be harmful in achieving metrological accuracies.
The protocol discussed here is limited to the realization of MOS nano-devices with metal gates. Therefore, to achieve full industrial compatibility and reduce charge fluctuations, it would be needed to modify the gate deposition techniques and use highly doped polycrystalline silicon as the gate material.
In conclusion, the MOS QD pumps discussed here have recently combined the technological advantage of silicon with very good performance in terms of accurate current generation13. This stems from the high flexibility of the design and fabrication process which allow one to stack multiple gate layers leading to a compact and versatile system. The resulting fine tunability of the electrostatic confinement of the dot together with the potential to reduce background charge fluctuations sets the stage to overcome the main challenges observed in other semiconductor pumps22,23 .

Silicon is the material of choice for most of the modern microelectronics. Its properties, combined with advanced lithographic techniques, have allowed the semiconductor industry to achieve very large-scale integration and deliver billions of transistors per chip. The metal-oxide-semiconductor (MOS) technology1 has been the key of this relentless technological progress2. In brief, it is based on a selectively doped Si substrate which is thermally oxidized to grow a high quality SiO2 gate oxide on which a metal gate electrode is deposited. Recently, it has been shown that the use of a stack of gate oxides could be beneficial3 . While present industry standards have reached minimum feature sizes for gate lengths below 20 nm, it is becoming increasingly evident that, at this level of miniaturization, detrimental quantum mechanical phenomena come into play that may complicate further downscaling4.
Remarkably, silicon is also an excellent host material to exploit the quantum properties of the electron charge and spin5. This has broadened its range of applicability to entirely new fields such as quantum computing6 and quantum electrical metrology7. Among other approaches5, the use of a multi-gate MOS technology8,9 has led to electrostatically-defined quantum dots (QD) whose occupancy can be controlled down to single-electron level10. Unlike the conventional MOS process where just one gate per transistor is needed1, these QDs are defined via a three-layer stack of Al/AlyOx gates which are used to selectively accumulate electrons at the Si/SiO2 interface, as well as provide lateral and vertical confinement11.
Although these devices had been originally developed for quantum computing applications, they have also recently shown promising performances as metrological tools12,13. In the field of quantum electrical metrology, a long-standing goal is the redefinition of the unit ampere in terms of the elementary charge (e) 14. In particular, the emphasis is on the realization of nano-scale charge pumps to clock the transfer of individual electrons timely and accurately. These devices generate macroscopic quantized electric currents, I=nef, where f is the frequency of an external driving oscillator and n is an integer. To date, the best performance has been achieved with a GaAs-based pump by yielding a current in excess of 150 pA with a relative uncertainty of 1.2 parts per million15. Recently, silicon MOS QDs have also stood out for the implementation of highly accurate single-electron pumps thanks to the capability of finely tuning the charge confinement13.
Here, we discuss the protocol used for the fabrication of silicon MOS QDs. Furthermore, the cryogenic set-up used to test the integrity of the devices after fabrication and the one to perform charge pumping experiments are described. Finally, representative measurements of quantized electric current are reported.

<table border="0" cellpadding="0" cellspacing="0">
	<tbody>
		<tr>
			<td>Silicon wafers</td>
			<td>TOPSIL</td>
			<td></td>
			<td>4 inch</td>
		</tr>
		<tr>
			<td>Electron-beam lithography machine</td>
			<td>Raith gmbh</td>
			<td></td>
			<td>Raith 150two</td>
		</tr>
		<tr>
			<td>E-beam resist&#160;</td>
			<td>MicroChem gmbh</td>
			<td></td>
			<td>PMMA</td>
		</tr>
		<tr>
			<td>Photoresist</td>
			<td>MicroChem gmbh</td>
			<td></td>
			<td>nLOF2020</td>
		</tr>
		<tr>
			<td>Mask aligner</td>
			<td>Quintel</td>
			<td></td>
			<td>Q6000</td>
		</tr>
		<tr>
			<td>Photoresist developer</td>
			<td>MicroChem gmbh</td>
			<td></td>
			<td>AZ826MIF</td>
		</tr>
	</tbody>
</table>

silicon metal-oxide-semiconductor quantum dots for single-electron pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

Device Fabrication
The initial microfabrication process (sub-section 1 of the Protocol) is performed on a commercial 4-inch high-purity silicon wafer (n-type doping concentration &#8776; 1012 cm-3; resistivity &#62; 10 k&#937;cm; thickness = 310&#8211;340 &#956;m). The aim is to realize the substrate on which the gate electrodes will be deposited. This substrate is made of an intrinsic region capped with field oxide (step 1.1), an n+ region capped with field oxide (step 1.2), an intrinsic region capped with high-quality gate oxide (step 1.3), and a metallized n+ region for ohmic contacts (step 1.4). Figures 1A-D&#160;illustrate the main steps of the microfabrication process. Figure 1E shows a microscopic image of a substrate field after microfabrication. The minimum feature size for the lithography at this stage is approximately 4 &#956;m.
The SiO2 oxide layer grown in step 1.1 has a nominal thickness of 100 nm and is used as a passivation layer. The n-type regions that act as ohmic conductors are obtained via phosphorus diffusion. The target doping density is approximately 1019 &#8211; 1020 cm-3. The high-quality SiO2 which is selectively grown to be used as gate dielectric has a nominal thickness of 5 nm. The target interface defect density is &#60;1010 eV-1cm-2 at mid-gap. A dedicated and purposely built triple wall furnace is used for this process. This system is designed to minimize contamination from heavy metal ions and mobile alkali ions, as well as prevent moisture from diffusing into the oxidation chamber. In order to form the electrical contacts, aluminum pads are deposited via electron-beam evaporation on part of the n-type regions.
The nanofabrication process (see sub-section 2) is performed on chip substrates obtained by dicing the wafer processed in step 1. The aim is to realize the nano-scale gate electrodes used to electrostatically define the MOS QDs. Each nanofabrication run typically produces 10&#8211;15 complete device samples. Scanning electron micrograph (SEM) imaging of 1&#8211;2 devices per batch is usually carried out to confirm that the EBL lithography stages have been successful. Since SEM imaging may inject charges in the substrate or in the metallic gates and cause leakages, only a small number of devices is checked in this way, while the rest is electrically tested. Minimum feature size for the lithography at this stage is approximately 35 nm. To achieve good uniformity of the deposited Al films, the metal is evaporated at rates as slow as few angstrom/second, while the substrate is mounted on a rotating stage. This is kept at RT, and the Al grain size is estimated to be of approximately 20 nm. Figure 2A illustrates the main steps of the nanofabrication process. Figure 2B shows a SEM image with which the correct definition of the gate electrodes is verified. In general, one aims at realizing those gates which directly define the QD (BL, BR and PL) with the smallest possible feature size. By contrast, those gates used to define the electron reservoirs (DL and SL) can have larger dimensions to avoid the unintentional discretization of energy levels in the leads. The nano-scale Ti/Pt markers realized in step 2.3 are used as reference for consistent alignment of the three layers of gates. Platinum is chosen for its excellent contrast with respect to the SiO2 surface in the e-beam. Titanium is used to enhance adhesion.
At all stages of the fabrication process, carbon-fiber-tip tweezers are used to handle the chips, in order to reduce the likelihood of destructive electrostatic discharge (ESD).
Finally, in order to perform electrical measurements on individual devices, each chip needs to be cleaved in smaller pieces of about 2 x 2 mm2 (sub-section 3). Each piece is then glued to a custom-made PCB (Rogers R03010 low-loss dielectric) whose pins are connected to the device electrodes through Al wires. Wire bonding is carried out with a wedge bonder machine without heating the chips. The choice of the appropriate bonding parameters is based on two considerations. On the one hand, the wire bond needs to perforate the thermal AlyOx layer and make good metal-to-metal contact with the gate pad. On the other hand, an excessive mechanical stress may result in a punch-trough event which damages the field oxide underneath the gate and cause substrate leakages. During the wiring process, the use of an antistatic bracelet is advisable to prevent ESD. In Figure 3, a chip with 6 individual devices is glued onto the PCB.
Device integrity tests
Before loading a device into a mK temperature measurement platform such as a dilution refrigerator, preliminary electrical tests are performed at 4.2 K to check the integrity of the sample (see sub-section 4 of the Protocol). To this end, the PCB is inserted into an oxygen-free copper enclosure and is mounted onto a dip probe, which is eventually immersed in liquid He.
The initial test is typically a leakage test that is performed sequentially on each gate. A source-measure unit is connected to an individual gate electrode while the others are grounded. The voltage is ramped up to 1.5 V and the current is measured at the source. Within this voltage range, a properly working gate is not supposed to conduct, because the SiO2 layer insulates the metal from the silicon substrate and AlyOx insulates overlapping gates. Typically, oxide breakdown is known to occur for voltages larger than ~4 V, depending on device geometry and oxide thickness. Therefore, if current is detected during the test, it is likely that at least one of the oxide layers is damaged and the device has to be discarded. Usually, less than 10% of the gates show leakages. The yield is known to be affected by the planar extension of the gate electrodes. In particular, the larger the overlap of the gates with the gate oxide region the more likely it will be to have gate-to-substrate leakages. Similarly, the larger the overlap between gates from different layers the more likely the occurrence of gate-to-gate leakages will be. The quoted yield is relevant for gates that occupy an area of about 50 &#956;m2 on the thin oxide and with interlayer overlaps of approximately 0.5 &#956;m2.
Once the device has passed the initial leakage test, the source and drain contacts are connected to a lock-in amplifier and the gates to a modular controllable-voltage battery rack. In this configuration, the device is turned on by globally ramping up all the gate voltages simultaneously. Next, each gate voltage is separately ramped down while keeping the others at high voltages to verify the ability of individual gates to pinch off the current. Figure 4A shows representative traces of these measurements. The absence of either a source-drain conduction pathway or individual gate pinch-off is often an indication of some type of gate damage such as gate explosion or metal discontinuity.
Finally, the source-drain current is measured as a function of source-drain bias and plunger gate voltage to observe the signature of Coulomb blockade16 (see Figure 4B).
Measurements
Once a suitable device has been found, it is removed from the liquid He vessel, and dried with a hot-air gun to avoid formation of moisture which may cause ESD. Finally, it is transferred to a dilution refrigerator.
The experiments are performed in a self-made plastic dilution refrigerator with a base temperature of about 100 mK. The cryostat is in a vacuum chamber immersed in a 4.2 K helium bath. The electrical lines are thermalized at the 1 K pot which is also employed to condense the incoming 3He vapor. In the mixing chamber, the endothermic transfer of 3He atoms from the 3He-rich phase into the 3He-dilute phase allows the system to reach a base temperature of about 100 mK.
As shown in Figure 5, the fridge is equipped with 20 dc lines and 3 rf lines used to connect the room-temperature electronics to the device at low temperature. Five of the dc lines are Thermocoax cables and 15 are twisted pair loom wires. These lines connect the gate electrodes of the sample to battery-powered dc voltage sources. Voltage dividers at RT are used to reduce electrical noise on individual gates. The RF lines are semirigid coaxial cables that are attenuated by 10 dB at 4 K to reduce thermal noise and dc blocked at RT. These lines are connected to the coplanar waveguides of the bias tees on the PCB.
A low-noise transimpedance amplifier and a digital multimeter are used to measure the current generated by the pump. The electronics is connected to the device via battery-powered optoisolators to prevent the formation of ground loops. The RF drive signals are produced by an arbitrary waveform generator whose grounding is isolated from the one of the cryostat via a dc block component (see Figure 5).
The PCB contains 16 pure dc lines and 4 bias tee lines used to combine dc and ac voltages at low temperature. As shown in Figure 3B, RC discrete components are used to realize the tee connection (R = 100 k&#937;, C = 10 nF), and 50 &#937;-matched integrated coplanar waveguides are used for the propagation of high-frequency signals.
Once the device is at mK temperature, the gate voltages are adjusted so that single-electron occupancy in the QD is attained. In particular, tunnel barriers are formed under gates BL and BR, and an electron accumulation layer is induced under gates PL, SL and DL. To this end, the barrier gate voltages are set below their turn-on values, while the accumulation gates are polarized at a greater-than-turn-on voltage. In this way a QD is formed under gate PL and its planar extension is controlled via gates C1 and C2 whose voltages are kept below their turn-on values to induce electrostatic confinement. Next, the rf signals are turned on to periodically modulate the transparency of the tunnel barrier(s), and the electrochemical potential of the dot. Single-electron pumping is achieved with either one or two sinusoidal driving voltages. In the case of one-signal drive, the driving signal is applied to gate BL to modulate the potential of the tunnel barrier at the left-hand-side of the QD. In the case of the two-signal drive, the ac excitations are applied to gates BL and PL to modulate the potentials of both the left barrier and the QD at the same frequency but with different phases and amplitudes. These additional degrees of freedom allow one to control the direction of the electron transfer13. An iterative process is typically needed to tune the main experimental parameters (i.e., rf drive signal amplitudes/phases and dc gate voltages) and achieve optimal current quantization. Note that neither of the two pumping protocols needs a drain-source bias to perform charge transfers. Hence, the source and drain electrodes are grounded during the pump operation. Figure 6 shows the characteristic current plateaux at integer multiples of ef obtained by applying a two-signal sinusoidal drive to the input barrier (BL) and the plunger (PL) gate. These data are taken at a relatively low driving frequency (10 MHz) for which the tuning of the parameters can be carried out fast. In practice, it is desirable to operate the pump at several hundreds of MHz, typically requiring a much finer parameter optimization13.
<img alt="Figure 1" src="/files/ftp_upload/52852/52852fig1.jpg" /> 
Figure 1. Microfabrication. (A) Schematic illustration of main steps in microfabrication. Cartoons are not drawn to scale. (B) Realization of a doped region for ohmic contacts. (C) Realization of gate oxide. (D) Metallization of ohmic contacts. (E) Microscopic image of an individual field on a chip after the microfabrication process is completed. Field size is 1.2 x 1.2 mm2. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig1large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 2" src="/files/ftp_upload/52852/52852fig2.jpg" /> 
Figure 2. Nanofabrication. (A) Fabrication process for individual gate layers. Cartoons are not drawn to scale. (B) The 3-layer gate nanostructure used for charge pumping experiments. Left: SEM image of a device similar to the one used for the measurements. Right: Schematic cross-sectional views of the device across X-cut and Y-cut. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig2large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 3" src="/files/ftp_upload/52852/52852fig3.jpg" /> 
Figure 3. Electrical connections to the sample. (A) Layout of the printed circuit board. (B) Magnification of a region of the PCB with a bias-tee (left) and equivalent circuit (right). (C) A chip with 6 individual fields glued on the chip holder and bond wires for electrical connection to the PCB. (D) Microscopic image of an individual field after nanofabrication. (E) SEM image of the gate layout at the center of the gate oxide region. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig3large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 4" src="/files/ftp_upload/52852/52852fig4.jpg" /> 
Figure 4. Preliminary tests. (A) Source-drain ac current (root mean square) as a function of different gate voltages. Traces are measured with a lock-in amplifier with 50 &#956;VRMS excitation at 113.17 Hz. For individual gate voltage traces the remaining gate voltages are fixed at 2.0 V, except for VC1 = VC2 = 0.0 V. (B) Color map of source-drain current as a function of plunger gate voltage and source-drain bias voltage. VSL = 1.5 V, VDL = 1.15 V, VBL = 0.78 V, VBR = 0.85 V, VC1 = VC2 = 0.0 V. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig4large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 5" src="/files/ftp_upload/52852/52852fig5.jpg" /> 
Figure 5. Schematic of the measurement set-up. Twenty dc lines (green) and three coaxial rf lines (black) connect the RT electronics to the PCB. The drain of the pump (purple) is connected to a transimpedance amplifier and to a digital multimeter via an optoisolator, while the source contact (red) is grounded. Separate ground connections (indicated with different symbols) are used for the electronic instrumentation and the cryostat electric lines. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig5large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 6" src="/files/ftp_upload/52852/52852fig6.jpg" /> 
Figure 6. Current quantization. Pumped current as a function of VPL for two-signal sinusoidal drive at f = 10 MHz applied to gates BL and PL. Phase difference = 49 deg, VRFPL = VRFBL = 0.31 Vpp. The ideal position of the pumping plateaux at integer multiples of ef are shown as red horizontal lines. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig6large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>

Watch this Scientific Journal Video about Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping at JoVE.com

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

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14.3K 조회수.  University of New South Wales. The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

비디오: Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Compact Quantum Dots for Single-molecule Imaging

Single-molecule imaging is an important tool for understanding the mechanisms of biomolecular function and for visualizing the spatial and temporal heterogeneity of molecular behaviors that underlie cellular biology 1-4. To image an individual molecule of interest, it is typically conjugated to a fluorescent tag (dye, protein, bead, or quantum dot) and observed with epifluorescence or total internal reflection fluorescence (TIRF) microscopy. While dyes and fluorescent proteins have been the mainstay of fluorescence imaging for decades, their fluorescence is unstable under high photon fluxes necessary to observe individual molecules, yielding only a few seconds of observation before complete loss of signal. Latex beads and dye-labeled beads provide improved signal stability but at the expense of drastically larger hydrodynamic size, which can deleteriously alter the diffusion and behavior of the molecule under study.
Quantum dots (QDs) offer a balance between these two problematic regimes. These nanoparticles are composed of semiconductor materials and can be engineered with a hydrodynamically compact size with exceptional resistance to photodegradation 5. Thus in recent years QDs have been instrumental in enabling long-term observation of complex macromolecular behavior on the single molecule level. However these particles have still been found to exhibit impaired diffusion in crowded molecular environments such as the cellular cytoplasm and the neuronal synaptic cleft, where their sizes are still too large 4,6,7.
Recently we have engineered the cores and surface coatings of QDs for minimized hydrodynamic size, while balancing offsets to colloidal stability, photostability, brightness, and nonspecific binding that have hindered the utility of compact QDs in the past 8,9. The goal of this article is to demonstrate the synthesis, modification, and characterization of these optimized nanocrystals, composed of an alloyed HgxCd1-xSe core coated with an insulating CdyZn1-yS shell, further coated with a multidentate polymer ligand modified with short polyethylene glycol (PEG) chains (Figure 1). Compared with conventional CdSe nanocrystals, HgxCd1-xSe alloys offer greater quantum yields of fluorescence, fluorescence at red and near-infrared wavelengths for enhanced signal-to-noise in cells, and excitation at non-cytotoxic visible wavelengths. Multidentate polymer coatings bind to the nanocrystal surface in a closed and flat conformation to minimize hydrodynamic size, and PEG neutralizes the surface charge to minimize nonspecific binding to cells and biomolecules. The end result is a brightly fluorescent nanocrystal with emission between 550-800 nm and a total hydrodynamic size near 12 nm. This is in the same size range as many soluble globular proteins in cells, and substantially smaller than conventional PEGylated QDs (25-35 nm).

We describe the preparation of colloidal quantum dots with minimized hydrodynamic size for single-molecule fluorescence imaging. Compared to conventional quantum dots, these nanoparticles are similar in size to globular proteins and are optimized for single-molecule brightness, stability against photodegradation, and resistance to nonspecific binding to proteins and cells.

단일 분자 이미징을위한 소형 양자 점

Single-molecule imaging is an important tool for  understanding the mechanisms of biomolecular function and for visualizing the  spatial and temporal ...

연구

공학

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient echo memory (GEM) is a protocol for storing optical quantum states of light in atomic ensembles. The primary motivation for such a technology is that quantum key distribution (QKD), which uses Heisenberg uncertainty to guarantee security of cryptographic keys, is limited in transmission distance. The development of a quantum repeater is a possible path to extend QKD range, but a repeater will need a quantum memory. In our experiments we use a gas of rubidium 87 vapor that is contained in a warm gas cell. This makes the scheme particularly simple. It is also a highly versatile scheme that enables in-memory refinement of the stored state, such as frequency shifting and bandwidth manipulation. The basis of the GEM protocol is to absorb the light into an ensemble of atoms that has been prepared in a magnetic field gradient. The reversal of this gradient leads to rephasing of the atomic polarization and thus recall of the stored optical state. We will outline how we prepare the atoms and this gradient and also describe some of the pitfalls that need to be avoided, in particular four-wave mixing, which can give rise to optical gain.

The gradient echo memory is a protocol for storing optical quantum states of light in atomic ensembles. Quantum memory is a key element of a quantum repeater, which can extend the range of quantum key distribution. We outline the operation of the scheme when implemented in a 3-level atomic ensemble.

온난 한 원자 증기의 그라데이션 에코 양자 메모리

Gradient  echo memory (GEM) is a protocol for storing optical quantum states of light in  atomic ensembles. The primary motivation for such a technology ...

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

게이트 정의 갈륨 비소 / AlGaAs 측면 양자점 나노

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Scanning-probe Single-electron Capacitance Spectroscopy

The integration of low-temperature scanning-probe techniques and single-electron capacitance spectroscopy represents a powerful tool to study the electronic quantum structure of small systems - including individual atomic dopants in semiconductors. Here we present a capacitance-based method, known as Subsurface Charge Accumulation (SCA) imaging, which is capable of resolving single-electron charging while achieving sufficient spatial resolution to image individual atomic dopants. The use of a capacitance technique enables observation of subsurface features, such as dopants buried many nanometers beneath the surface of a semiconductor material1,2,3. In principle, this technique can be applied to any system to resolve electron motion below an insulating surface.
As in other electric-field-sensitive scanned-probe techniques4, the lateral spatial resolution of the measurement depends in part on the radius of curvature of the probe tip. Using tips with a small radius of curvature can enable spatial resolution of a few tens of nanometers. This fine spatial resolution allows investigations of small numbers (down to one) of subsurface dopants1,2. The charge resolution depends greatly on the sensitivity of the charge detection circuitry; using high electron mobility transistors (HEMT) in such circuits at cryogenic temperatures enables a sensitivity of approximately 0.01 electrons/Hz&frac12; at 0.3 K 5.

Scanning-probe single-electron capacitance spectroscopy facilitates the study of single-electron motion in localized subsurface regions. A sensitive charge-detection circuit is incorporated into a cryogenic scanning probe microscope to investigate small systems of dopant atoms beneath the surface of semiconductor samples.

스캐닝 프로브 단일 전자 용량 분광학

The integration of low-temperature scanning-probe techniques and single-electron capacitance spectroscopy represents a powerful tool to study the ...

Analysis of Contact Interfaces for Single GaN Nanowire Devices

Single GaN nanowire (NW) devices fabricated on SiO2 can exhibit a strong degradation after annealing due to the occurrence of void formation at the contact/SiO2 interface. This void formation can cause cracking and delamination of the metal film, which can increase the resistance or lead to a complete failure of the NW device. In order to address issues associated with void formation, a technique was developed that removes Ni/Au contact metal films from the substrates to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN NW devices. This procedure determines the degree of adhesion of the contact films to the substrate and NWs and allows for the characterization of the morphology and composition of the contact interface with the substrate and nanowires. This technique is also useful for assessing the amount of residual contamination that remains from the NW suspension and from photolithographic processes on the NW-SiO2 surface prior to metal deposition. The detailed steps of this procedure are presented for the removal of annealed Ni/Au contacts to Mg-doped GaN NWs on a SiO2 substrate.

A technique was developed that removes Ni/Au contact metal films from their substrate to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN nanowire devices.

단 하나의 GaN 나노 와이어 장치에 대한 문의 인터페이스의 분석

Single GaN nanowire (NW) devices fabricated on SiO2 can exhibit  a strong degradation after annealing due to the  occurrence of void formation at the ...

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms.
In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station.

A detailed procedure for surface doping of Silicon interfaces is provided. The ultra-shallow surface doping is demonstrated by using phosphorus containing monolayers and rapid annealing process. The method can be used for doping of macroscopic area surfaces as well as nanostructures.

유기 화합물을 사용하여 실리콘 표면과 나노 와이어의 단층 연락 도핑

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

실리콘 다이렉트 웨이퍼 본딩을 통한 균일한 나노스케일 캐비티 제조

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Construction and Characterization of External Cavity Diode Lasers for Atomic Physics

Since their development in the late 1980s, cheap, reliable external cavity diode lasers (ECDLs) have replaced complex and expensive traditional dye and Titanium Sapphire lasers as the workhorse laser of atomic physics labs1,2. Their versatility and prolific use throughout atomic physics in applications such as absorption spectroscopy and laser cooling1,2 makes it imperative for incoming students to gain a firm practical understanding of these lasers. This publication builds upon the seminal work by Wieman3, updating components, and providing a video tutorial. The setup, frequency locking and performance characterization of an ECDL will be described. Discussion of component selection and proper mounting of both diodes and gratings, the factors affecting mode selection within the cavity, proper alignment for optimal external feedback, optics setup for coarse and fine frequency sensitive measurements, a brief overview of laser locking techniques, and laser linewidth measurements are included.

This is an instructional paper to guide the construction and diagnostics of external cavity diode lasers (ECDLs), including component selection and optical alignment, as well as the basics of frequency reference spectroscopy and laser linewidth measurements for applications in the field of atomic physics.

원자 물리학에 대한 외부 공동 다이오드 레이저의 구조 및 특성

Since their development in the late 1980s, cheap, reliable external cavity diode lasers (ECDLs) have replaced complex and expensive traditional dye and ...

Selective Area Modification of Silicon Surface Wettability by Pulsed UV Laser Irradiation in Liquid Environment

The wettability of silicon (Si) is one of the important parameters in the technology of surface functionalization of this material and fabrication of biosensing devices. We report on a protocol of using KrF and ArF lasers irradiating Si (001) samples immersed in a liquid environment with low number of pulses and operating at moderately low pulse fluences to induce Si wettability modification. Wafers immersed for up to 4 hr in a 0.01% H2O2/H2O solution did not show measurable change in their initial contact angle (CA) ~75&#176;. However, the 500-pulse KrF and ArF lasers irradiation of such wafers in a microchamber filled with 0.01% H2O2/H2O solution at 250 and 65 mJ/cm2, respectively, has decreased the CA to near 15&#176;, indicating the formation of a superhydrophilic surface. The formation of OH-terminated Si (001), with no measurable change of the wafer&#8217;s surface morphology, has been confirmed by X-ray photoelectron spectroscopy and atomic force microscopy measurements. The selective area irradiated samples were then immersed in a biotin-conjugated fluorescein-stained nanospheres solution for 2 hr, resulting in a successful immobilization of the nanospheres in the non-irradiated area. This illustrates the potential of&#160;the method for selective area biofunctionalization and fabrication of advanced Si-based biosensing architectures. We also describe a similar protocol of irradiation of wafers immersed in methanol (CH3OH) using ArF laser operating at pulse fluence of 65 mJ/cm2 and in situ formation of a strongly hydrophobic surface of Si (001) with the CA of 103&#176;. The XPS results indicate ArF laser induced formation of Si&#8211;(OCH3)x compounds responsible for the observed hydrophobicity. However, no such compounds were found by XPS on the Si surface irradiated by KrF laser in methanol, demonstrating the inability of the KrF laser to photodissociate methanol and create -OCH3 radicals.

We report on a process of in situ alteration of HF treated Si (001) surface into a hydrophilic or hydrophobic state by irradiating samples in microfluidic chambers filled with&#160;H2O2/H2O solution (0.01%-0.5%) or methanol solutions using pulsed UV laser of a relative low pulse fluence.

액체 환경에서의 펄스 자외선 레이저 조사에 의한 실리콘 표면의 젖음성의 선택 영역 수정

The wettability of silicon (Si) is one of the important parameters in the technology of surface functionalization of this material and fabrication of ...

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

A procedure to measure the bulk lifetime (&#62;100 &#181;sec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min&#160;using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (&#60;1012 cm-3).

A RT liquid surface passivation technique to investigate the recombination activity of bulk silicon defects is described. For the technique to be successful, three critical steps are required: (i) chemical cleaning and etching of silicon, (ii) immersion of silicon in 15% hydrofluoric acid and (iii) illumination for 1 min.

향상된 광 불산 패시베이션 : 벌크 실리콘 결함을 검출하기위한 민감한 기술

A procedure to measure the bulk lifetime (&#62;100 &#181;sec) of silicon wafers by temporarily attaining a very high level of surface passivation when ...