Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Caution: Please consult all relevant material safety data sheets (MSDS) before use. Several of the chemicals used in this fabrication process are acutely toxic and carcinogenic. Nanomaterials may have additional hazards compared to their bulk counterpart. Please use all appropriate safety practices when working with equipment, chemicals or nanomaterials, including the use of engineering controls (fume hood) and personal protective equipment (safety glasses, gloves, cleanroom clothes).
1. Alignment Marker Definition for Lithography
<ol>
	<li>Start with single-sided polished industrial grade Si(100) wafers with either n or p-type doping.</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist. Perform a 90 sec hexamethyldisilazane (HMDS) treatment at 130 &#176;C to promote adhesion of the photoresist, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the alignment markers, exposure dose 120 mJ/cm2.</li>
	<li>Perform a single puddle development process. Perform a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C to cure the resist.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions.</li>
	<li>Etch 120 nm of Si using chlorine plasma etching. This thickness gives good contrast for the automatic alignment systems of the exposure tool used in this work. For example using an inductive coupled plasma (ICP): 20/40 sccm O2/CF4, 5 mTorr, 60/500 W platen/ICP RF power, 10 sec oxide breakthrough etching, followed by 80/40 sccm Cl2/HBr, 60 mTorr, 20/500 W platen/ICP RF power, 35 sec Si etch.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). As the photoresist is cured by the plasma normal solvent like acetone cannot be used.</li>
	<li>Clean the wafers. First put them for 10 min in 99% HNO3, followed by rinsing in DI water till the resistivity of the water is 5 M&#937; (organic clean). After this clean the wafers for 10 min in 65% HNO3 at 110 &#176;C, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (metal clean). Use a rinser dryer to dry the wafers.</li>
</ol>
2. Bottom Metal and Interlayer Dielectric Deposition
<ol>
	<li>Use magnetron sputtering to deposit the bottom metal layer of the test via. A stack of three metal layers needs to be deposited: 500 nm of Ti, 50 nm of TiN, and 100 nm Ti. The first Ti layer is to reduce the resistance of the stack, the TiN is the actual support layer for CNT growth, and the top Ti is to protect the TiN against plasma damage when etching the SiO2 layer12. Perform Ti sputtering using a pure Ti target with Ar-plasma at a substrate temperature of 350 &#176;C. For TiN reactive sputtering use a combination of Ar and N2, again at 350 &#176;C substrate temperature.</li>
	<li>Using plasma-enhanced chemical vapor deposition (PECVD), deposit a 1 &#181;m thick layer of SiO2. Here tetraethyl orthosilicate (TEOS) is used as precursor at a platen temperature of 350 &#176;C.
	<ol>
		<li>Check the thickness of the SiO2 layer using an appropriate tool, for instance a reflectometer or ellipsometer.</li>
	</ol>
	</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool, expose the desired pattern of openings, which will be later etched into the SiO2 to form the vias, aligned to the alignment markers, exposure dose 140 mJ/cm2.</li>
	<li>Perform a single puddle development process starting with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions and if the overlay to the alignment markers is correct.</li>
	<li>Plasma etch the contact openings in the SiO2. For example, use a triode plasma etcher with C2F6/CHF3 36/144 sccm at 180 mTorr and 300 W RF power. If necessary, perform etch rate tests on a test wafer in order to minimize over etching to 5%-10% in time. 
	Note: Although the Ti is resistant to reactive etching in this fluorine chemistry, prolonged exposure to the plasma will result in physical etching of the Ti layer. If the TiN layer is exposed to the plasma this will have a negative influence on the growth of the CNT12. Do not use wet etching as this will result in too much widening of the openings, making the top metallization in part 4 problematic.</li>
	<li>Remove the sacrificial Ti layer by wet etching in 0.55% HF for 60 sec. After etching rinse the wafers with DI water till the water resistivity is 5 M&#937; and use a rinser dryer to dry the wafers. 
	Note: Using a microscope it can be checked if the Ti layer is etched, the TiN layer will have a gold-brown color while the Ti is metallic grey.</li>
</ol>
3. Catalyst Deposition and CNT Growth
<ol>
	<li>Evaporate 5 nm of Co using an e-beam evaporator. Pump down till at least 2x10-6 Torr, and heat the wafers to 60 &#176;C using lamps under vacuum before depositing to remove any water film. The photo-resist used to define the contact openings is kept on the wafer to provide self-alignment of the catalyst to the contact openings in the SiO2.</li>
	<li>Remove the Co outside the contact openings by lift-off. For Co it was found that tetrahydrofuran (THF) gives the best lift-off results and growth at low temperatures. N-methyl-2-pyrrolidone (NMP), which was previously used for lift-off after Fe evaporation, was found to damage the Co too such an extent to prevent any aligned CNT growth. Put the wafer for 15 min in an ultrasonic bath with THF at 35 &#176;C. Rinse with DI water for 5 min and dry using a spinner or nitrogen gun.</li>
	<li>Inspect the wafer underneath a microscope and check for resist residues. If residues remain perform a longer ultrasonic treatment in THF, and optionally use a special soft cotton swab for lift-off purposes to manually wipe away residues.</li>
	<li>Perform CNT growth using low-pressure chemical vapor deposition (LPCVD). Use the following recipe: 8 min pre-anneal at 350 &#176;C with 700 sccm H2 at 80 mbar, followed by CNT growth by adding 50 sccm C2H2. At 350 &#176;C, 60 min of growth gives roughly 1 &#181;m of CNT. If necessary perform a test growth to tune the height, which should be the same thickness as the SiO2 layer. Cool down the reactor and purge using N2.</li>
	<li>Use a scanning electron microscope to check the height of the CNT inside the openings under 45&#176; tilt, or by preparing a cross-section.</li>
	<li>Inspect the samples using Raman spectroscopy to determine the crystallinity of the CNT18.</li>
</ol>
4. Topside Metallization
<ol>
	<li>Use magnetron sputtering to deposit the top metal. As Ti is a good metal for contacting CNT19, first sputter 100 nm of Ti, followed by 2 &#181;m of Al (1% Si) without breaking the vacuum.</li>
	<li>Coat the wafer with 3.1 &#181;m of positive photoresist with higher viscosity, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at 3,000 rpm, and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the top metal pattern aligned to the alignment markers, exposure dose 420 mJ/cm2, focus of -1.</li>
	<li>Perform a single puddle development process. This starts with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the lines in the resist are of the correct dimensions and if the overlay to the markers is correct.</li>
	<li>Etch the Ti/Al stack using chlorine plasma etching. For example using an inductive coupled plasma: 30/40 sccm Cl2/HBr, 5 mTorr, 40/500 W Platen/ICP RF power with endpoint detection and 80% overetch using 15/30 sccm Cl2/HBr.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). If the metal coverage is not complete (i.e., there are pinholes around the CNT) use an organic solvent (e.g., NMP) to remove the photoresist in order to prevent plasma damage to the CNT.</li>
	<li>Clean the wafers. Put them for 10 min in 99% HNO3, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (organic clean). Use a rinser dryer to dry the wafers.</li>
</ol>
5. Measurements
<ol>
	<li>Use a scanning electron microscope according to manufacturer&#39;s instructions to check the top metallization of the wafers. 
	Note: If necessary the wafer can be mechanically cleaved in order to check the complete CNT via using a sample tilt of 90&#176;, resulting in images as shown in Figure 3. As the samples are electrically conductive no additional treatment steps have to be used and the samples can be directly mounted into the SEM. Generally, high acceleration voltages of 15 or 20 kV can be used, but if the SiO2 layer is charging up too much this can be reduced to 5 kV.</li>
	<li>Perform 4-point probe I-V measurements using a probe station in combination with a semiconductor parameter analyzer as described in Figure 1 and in Vollebregt et al. 16. 
	Note: Normally a voltage sweep from -0.5 to 0.5 V is sufficient, as the potential drop over an interconnect ideally is small. By using a 4-point probe setup the contact resistance of the probe needles and the wire resistances of the setup are omitted.</li>
</ol>

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The authors have nothing to disclose.

Figure 1 displays a schematic overview of the structure fabricated in this work, and which was used for the 4-point probe measurements. As the potential is measured through probes carrying no current, the exact potential drop (VH-VL) over the central CNT bundle and its contacts to the metal can be measured. Bigger diameter CNT bundles are used to contact the bottom TiN layer from the contact pads, in order to reduce the total resistance for the current forcing probes and maximize th...

Copper and tungsten, the metals which are currently used for the interconnects in state-of-the-art very-large-scale integration (VLSI) technology, are approaching their physical limits in terms of reliability and electrical conductivity1. While down-scaling transistors generally improves their performance, it actually increases the resistance and current density of the interconnects. This resulted in interconnects dominating the integrated circuit (IC) performance in terms of delay and power consumption2.
Carbon nanotubes (CNT) have been suggested as alternative for Cu and W metallization, especially for vertical interconnects (vias) as CNT can easily been grown vertical3. CNT have been shown to have excellent electrical reliability, allowing an up to 1,000 times higher current density than Cu4. Moreover, CNT do not suffer from surface and grain boundary scattering, which is increasing the resistivity of Cu at the nanometer scale5. Finally, CNT have been shown to be excellent thermal conductors6, which can aid in the thermal management in VLSI chips.
For successful integration of CNT in VLSI technology it is important that the growth processes for the CNT is made compatible with semiconductor fabrication. This requires the low temperature growth of CNT (&#60; 400 &#176;C) using materials and equipment which are considered compatible and scalable to large scale manufacturing. While many examples of CNT test vias have been demonstrated in the literature7,8,9,10,11,12,13,14, most of these use Fe as catalyst which is regarded as a contaminant in IC manufacturing15. Besides, the growth temperature used in many of these works is much higher than the upper limit of 400 &#176;C. Preferably CNT should even be grown below 350 &#176;C, in order to allow integration with modern low-&#954; dielectrics or flexible substrates.
Here we present a scalable method for growing CNT at temperatures as low as 350 &#176;C using Co as catalyst16. This method is of interest for fabricating different electrical structures consisting of vertically aligned CNT in integrated circuits, ranging from interconnect and electrodes to super capacitors and field emission devices. The Co catalyst metal is often used in IC manufacturing for the fabrication of silicide&#8217;s17, while TiN is an often used barrier material7. Moreover, we demonstrate a process for fabricating CNT test vias while only using techniques from standard semiconductor manufacturing. With this, CNT test vias are fabricated, inspected by scanning electron microscopy (SEM) and Raman spectroscopy, and electrically characterized.

<table border="0" cellpadding="0" cellspacing="0" width="905">
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		<col />
		<col />
		<col />
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	<tbody>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Materials</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td style="width:291px;">Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Si (100) wafer 4&#34;</td>
			<td style="width:188px;">International Wafer Service</td>
			<td style="width:119px;"></td>
			<td>Resisitivity: 2-5 m&#937;-cm, thickness: 525 &#181;m&#160;</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Ti-sputtertarget (99.995 % purity)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Al (1% Si)-sputtertarget (99.999 % purity)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Co (99.95 % purity)</td>
			<td style="width:188px;">Kurt J. Lesker</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Chemicals</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPR3012 positive photoresist</td>
			<td style="width:188px;">Dow Electronic Materials</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">MF-322 developer</td>
			<td style="width:188px;">Dow Electronic Materials</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HNO3 (99.9 %)</td>
			<td style="width:188px;">KMG Ultra Pure Chemicals</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HNO3 (69.5%)</td>
			<td style="width:188px;">KMG Ultra Pure Chemicals</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HF 0.55%</td>
			<td style="width:188px;">Honeywell</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tetrahydrofuran</td>
			<td style="width:188px;">JT Baker</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Acetone</td>
			<td style="width:188px;">Sigma-Aldrich</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">ECI3027 positive photoresist</td>
			<td style="width:188px;">AZ</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tetraethyl orthosilicate (TEOS)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Gasses</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">N2 (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">O2 (99.9999%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CF4 (99.9970%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CL2 (99.9900%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">HBr (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Ar (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">C2F6 (99.9990%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CHF3 (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">H2 (99.9950%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">C2H2 (99.6000%)</td>
			<td style="width:188px;">Praxair</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Equipment</td>
			<td style="width:188px;">Company</td>
			<td style="width:119px;">Catalog Number</td>
			<td>Comments/Description</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">EVG 120 coater/developer</td>
			<td style="width:188px;">EVG</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">ASML PAS5500/80 waferstepper</td>
			<td style="width:188px;">ASML</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPTS &#937;mega 201 plasma etcher</td>
			<td style="width:188px;">SPTS</td>
			<td style="width:119px;"></td>
			<td>Used for Si and metal etching</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">SPTS &#931;igma sputter coater</td>
			<td style="width:188px;">SPTS</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Novellus Concept One PECVD</td>
			<td style="width:188px;">LAM</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Drytek 384T plasma etcher</td>
			<td style="width:188px;">LAM</td>
			<td style="width:119px;"></td>
			<td>Used for oxide etching</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">CHA Solution e-beam evaporator</td>
			<td style="width:188px;">CHA</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">AIXTRON BlackMagic Pro CVD tool</td>
			<td style="width:188px;">AIXTRON</td>
			<td style="width:119px;"></td>
			<td>Carbon nanotube growth</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Philips XL50 scanning electron microscope</td>
			<td style="width:188px;">FEI</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Tepla 300</td>
			<td style="width:188px;">PVA TePla</td>
			<td style="width:119px;"></td>
			<td>Resist plasma stripper</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Avenger rinser dryer</td>
			<td style="width:188px;">Microporcess Technologies</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Leitz MPV-SP reflecometer</td>
			<td style="width:188px;">Leitz</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Renishaw inVia Raman spectroscope</td>
			<td style="width:188px;">Renishaw</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Agilent 4156C parameter spectrum analyzer</td>
			<td style="width:188px;">Agilent</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:307px;">Cascade Microtech probe station</td>
			<td style="width:188px;">Cascade Microtech</td>
			<td style="width:119px;"></td>
			<td></td>
		</tr>
	</tbody>
</table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

The design of the measurement structure used in this work can be found in Figure 1. By employing such a structure the measurement of the CNT bundle resistance and the metal-CNT contact resistances can be determined accurately, as probe and wire resistances are circumvented. The resistance of the bundle is a measure for the quality and density of the CNT bundle. In order to determine the contact resistance bundles of different lengths should be measured.
A typical SEM image of ...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Research

JoVE Journal

Engineering

7.6K Views.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Video: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Synthesis and Functionalization of Nitrogen-doped Carbon Nanotube Cups with Gold Nanoparticles as Cork Stoppers

Nitrogen-doped carbon nanotubes consist of many cup-shaped graphitic compartments termed as nitrogen-doped carbon nanotube cups (NCNCs). These as-synthesized graphitic nanocups from chemical vapor deposition (CVD) method were stacked in a head-to-tail fashion held only through noncovalent interactions. Individual NCNCs can be isolated out of their stacking structure through a series of chemical and physical separation processes. First, as-synthesized NCNCs were oxidized in a mixture of strong acids to introduce oxygen-containing defects on the graphitic walls. The oxidized NCNCs were then processed using high-intensity probe-tip sonication which effectively separated the stacked NCNCs into individual graphitic nanocups. Owing to their abundant oxygen and nitrogen surface functionalities, the resulted individual NCNCs are highly hydrophilic and can be effectively functionalized with gold nanoparticles (GNPs), which preferentially fit in the opening of the cups as cork stoppers. These graphitic nanocups corked with GNPs may find promising applications as nanoscale containers and drug carriers.

We discussed the synthesis of individual graphitic nanocups using a series of techniques including chemical vapor deposition, acid oxidation and probe-tip sonication. By citrate reduction of HAuCl4, the graphitic nanocups were effectively corked with gold nanoparticles due to the chemically reactive edges of the cups.

Nitrogen-doped carbon  nanotubes consist of many cup-shaped graphitic compartments termed as  nitrogen-doped carbon nanotube cups (NCNCs).  These ...

Writing and Low-Temperature Characterization of Oxide Nanostructures

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions. Oxide interfaces exhibit a wide range of properties that can be controlled include conduction, piezoelectric behavior, ferromagnetism, superconductivity and nonlinear optical properties. Recently, methods for controlling these properties at extreme nanoscale dimensions have been discovered and developed. Here are described explicit step-by-step procedures for creating LaAlO3/SrTiO3 nanostructures using a reversible conductive atomic force microscopy technique. The processing steps for creating electrical contacts to the LaAlO3/SrTiO3 interface are first described. Conductive nanostructures are created by applying voltages to a conductive atomic force microscope tip and locally switching the LaAlO3/SrTiO3 interface to a conductive state. A versatile nanolithography toolkit has been developed expressly for the purpose of controlling the atomic force microscope (AFM) tip path and voltage. Then, these nanostructures are placed in a cryostat and transport measurements are performed. The procedures described here should be useful to others wishing to conduct research in oxide nanoelectronics.

Oxide nanostructures provide new opportunities for science and technology. The interfacial conductivity between LaAlO3 and SrTiO3 can be controlled with near-atomic precision using a conductive atomic force microscopy technique. The protocol for creating and measuring conductive nanostructures at LaAlO3/SrTiO3 interfaces is demonstrated.

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions.  Oxide ...

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal&#8211;semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 &#937;&#8722;1 cm&#8722;1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

We describe the approaches for the device fabrication and electrical characterization of molybdenum diselenide (MoSe2) layer semiconductor nanostructures with different thicknesses. In addition, the fabrication of ohmic contacts for MoSe2-layer nanocrystals by the focused-ion beam deposition method using platinum (Pt) as a contact metal is described.

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor ...

Advanced Experimental Methods for Low-temperature Magnetotransport Measurement of Novel Materials

Novel electronic materials are often produced for the first time by synthesis processes that yield bulk crystals (in contrast to single crystal thin film synthesis) for the purpose of exploratory materials research. Certain materials pose a challenge wherein the traditional bulk Hall bar device fabrication method is insufficient to produce a measureable device for sample transport measurement, principally because the single crystal size is too small to attach wire leads to the sample in a Hall bar configuration. This can be, for example, because the first batch of a new material synthesized yields very small single crystals or because flakes of samples of one to very few monolayers are desired. In order to enable rapid characterization of materials that may be carried out in parallel with improvements to their growth methodology, a method of device fabrication for very small samples has been devised to permit the characterization of novel materials as soon as a preliminary batch has been produced. A slight variation of this methodology is applicable to producing devices using exfoliated samples of two-dimensional materials such as graphene, hexagonal boron nitride (hBN), and transition metal dichalcogenides (TMDs), as well as multilayer heterostructures of such materials. Here we present detailed protocols for the experimental device fabrication of fragments and flakes of novel materials with micron-sized dimensions onto substrate and subsequent measurement in a commercial superconducting magnet, dry helium close-cycle cryostat magnetotransport system at temperatures down to 0.300 K and magnetic fields up to 12 T.

We describe the methodology of mechanical exfoliation and deposition of flakes of novel materials with micron-sized dimensions onto substrate, fabrication of experimental device structures for transport experimentation, and the magnetotransport measurement in a dry helium close-cycle cryostat at temperatures down to 0.300 K and magnetic fields up to 12 T.

Novel electronic materials are often produced for the first time by synthesis processes that yield bulk crystals (in contrast to single crystal thin film ...

Precision Milling of Carbon Nanotube Forests Using Low Pressure Scanning Electron Microscopy

A nanoscale fabrication technique appropriate for milling carbon nanotube (CNT) forests is described. The technique utilizes an environmental scanning electron microscope (ESEM) operating with a low pressure water vapor ambient. In this technique, a portion of the electron beam interacts with the water vapor in the vicinity of the CNT sample, dissociating the water molecules into hydroxyl radicals and other species by radiolysis. The remainder of the electron beam interacts with the CNT forest sample, making it susceptible to oxidation from the chemical products of radiolysis. This technique may be used to trim a selected region of an individual CNT, or it may be used to remove hundreds of cubic microns of material by adjusting ESEM parameters. The machining resolution is similar to the imaging resolution of the ESEM itself. The technique produces only small quantities of carbon residue along the boundaries of the cutting zone, with minimal effect on the native structural morphology of the CNT forest.

Low pressure scanning electron microscopy in a water vapor ambient is used to machine nanoscale to microscale features in carbon nanotube forests.

A nanoscale fabrication technique appropriate for milling carbon nanotube (CNT) forests is described. The technique utilizes an environmental scanning ...

High Temperature Fabrication of Nanostructured Yttria-Stabilized-Zirconia (YSZ) Scaffolds by In Situ Carbon Templating Xerogels

We demonstrate a method for the high temperature fabrication of porous, nanostructured yttria-stabilized-zirconia (YSZ, 8 mol% yttria - 92 mol% zirconia) scaffolds with tunable specific surface areas up to 80 m2&#183;g-1. An aqueous solution of a zirconium salt, yttrium salt, and glucose is mixed with propylene oxide (PO) to form a gel. The gel is dried under ambient conditions to form a xerogel. The xerogel is pressed into pellets and then sintered in an argon atmosphere. During sintering, a YSZ ceramic phase forms and the organic components decompose, leaving behind amorphous carbon. The carbon formed in situ serves as a hard template, preserving a high surface area YSZ nanomorphology at sintering temperature. The carbon is subsequently removed by oxidation in air at low temperature, resulting in a porous, nanostructured YSZ scaffold. The concentration of the carbon template and the final scaffold surface area can be systematically tuned by varying the glucose concentration in the gel synthesis. The carbon template concentration was quantified using thermogravimetric analysis (TGA), the surface area and pore size distribution was determined by physical adsorption measurements, and the morphology was characterized using scanning electron microscopy (SEM). Phase purity and crystallite size was determined using X-ray diffraction (XRD). This fabrication approach provides a novel, flexible platform for realizing unprecedented scaffold surface areas and nanomorphologies for ceramic-based electrochemical energy conversion applications, e.g. solid oxide fuel cell (SOFC) electrodes.

High Temperature Fabrication of Nanostructured Yttria-Stabilized-Zirconia YSZ Scaffolds by In Situ Carbon Templating Xerogels

A protocol for fabricating porous, nanostructured yttria-stabilized-zirconia (YSZ) scaffolds at temperatures between 1,000 &#176;C and 1,400 &#176;C is presented.

We demonstrate a method for the high temperature fabrication of porous, nanostructured yttria-stabilized-zirconia (YSZ, 8 mol% yttria - 92 mol% zirconia) ...

Fabrication of 3D Carbon Microelectromechanical Systems (C-MEMS)

A wide range of carbon sources are available in nature, with a variety of micro-/nanostructure configurations. Here, a novel technique to fabricate long and hollow glassy carbon microfibers derived from human hairs is introduced. The long and hollow carbon structures were made by the pyrolysis of human hair at 900 &#176;C in a N2 atmosphere. The morphology and chemical composition of natural and pyrolyzed human hairs were investigated using scanning electron microscopy (SEM) and electron-dispersive X-ray spectroscopy (EDX), respectively, to estimate the physical and chemical changes due to pyrolysis. Raman spectroscopy was used to confirm the glassy nature of the carbon microstructures. Pyrolyzed hair carbon was introduced to modify screen-printed carbon electrodes ; the modified electrodes were then applied to the electrochemical sensing of dopamine and ascorbic acid. Sensing performance of the modified sensors was improved as compared to the unmodified sensors. To obtain the desired carbon structure design, carbon micro-/nanoelectromechanical system (C-MEMS/C-NEMS) technology was developed. The most common C-MEMS/C-NEMS fabrication process consists of two steps: (i) the patterning of a carbon-rich base material, such as a photosensitive polymer, using photolithography; and (ii) carbonization through the pyrolysis of the patterned polymer in an oxygen-free environment. The C-MEMS/NEMS process has been widely used to develop microelectronic devices for various applications, including in micro-batteries, supercapacitors, glucose sensors, gas sensors, fuel cells, and triboelectric nanogenerators. Here, recent developments of a high-aspect ratio solid and hollow carbon microstructures with SU8 photoresists are discussed. The structural shrinkage during pyrolysis was investigated using confocal microscopy and SEM. Raman spectroscopy was used to confirm the crystallinity of the structure, and the atomic percentage of the elements present in the material before and after pyrolysis was measured using EDX.

Fabrication of 3D Carbon Microelectromechanical Systems C-MEMS

Long and hollow glassy carbon microfibers were fabricated based on the pyrolysis of a natural product, human hair. The two fabrication steps of carbon microelectromechanical and carbon nanoelectromechanical systems, or C-MEMS and C-NEMS, are: (i) photolithography of a carbon-rich polymer precursor and (ii) pyrolysis of the patterned polymer precursor.

A wide range of carbon sources are available in nature, with a variety of micro-/nanostructure configurations. Here, a novel technique to fabricate long ...

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...