Name: a standard and reliable method to fabricate two-dimensional nanoelectronics
Uploaded: 2018-08-28T13:00:00
Description: Watch this Scientific Journal Video about A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics at JoVE.com

This work was supported by the National Science Council, Taiwan under contract No. MOST 105-2112-M-003-016-MY3. This work was also in part supported by the National Nano Device Laboratories and e-beam laboratory in electrical engineering of National Taiwan University.

1. 2D Quasi-heterojunction Transistors Fabrication Process
<ol>
	<li>Prepare commercial c-plane sapphire.
	<ol>
		<li>Wash the whole single-side polished sapphire (2-inch) with acetone.</li>
		<li>Rinse the sapphire substrate with isopropyl alcohol.</li>
	</ol>
	</li>
	<li>Grow MoS2 on sapphire substrate using CVD in a hot-wall furnace.
	<ol>
		<li>Place 0.6 g of molybdenum trioxide (MoO3) powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstr...

<ol>
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In this article, the detailed procedures of fabricating novel electronics based on 2D materials in nanometer scale are demonstrated. Since the sample preparation procedures of each application have differences with each other, the overlapped processes were treated as the protocol. Electron beam patterning combined with material location determination and metal electrode definition thus serves as the protocol here. Among the two types of devices mentioned, the whole process of 2D back-gated transistors starting at wet tra...

Since past decades, mankind has been experiencing rapid downscale in the size of transistors and, consequently, an exponential increase in the number of transistors in integrated circuits (ICs). This maintains the continuous progress of silicon-based complementary metal-oxide semiconductor (CMOS) technology1. Moreover, this current trend in the size and performance of fabricated devices are still on-track with Moore&#39;s law, which states that the number of transistors on electronic chips, as well as their performance, doubles roughly every two years2. CMOS transistors are present in most, if not all, of the electronic devices available in the market and thus making it an integral part of human lives. Due to this, there are continuous demands for improvements in chip size and performance which have been pushing the manufacturers to keep following the Moore&#39;s law track.
Unfortunately, Moore&#39;s law appears to be nearing its end due to the amount of heat generated as more silicon circuitry is squeezed into a small area2. This calls for new types of materials that can provide the same, if not better, performance as silicon and, at the same time, can be implemented in a relatively smaller scale. Recently, new promising materials have been subjects of many material science researches. Such materials as one-dimensional (1D) carbon nanotubes3,4,5,6,7, 2D graphene8,9,10,11,12, and transition metal dichalcogenides (TMDs)13,14,15,16,17,18, are good candidates that can be used as substitute for the silicon-based CMOS and continue the Moore&#39;s law track.
Fabrication of small-scale devices requires careful determination of the material&#39;s location to successfully proceed to the other fabrication techniques such as lithography and metal electrode definition. So, the method presented in this paper was designed to address this need. Compared to the traditional semiconductor fabrication techniques19, the approach presented in this paper is tailor-fitted to the development of small-scale devices which needs more attention in terms of finding the location of the material. The aim of this method is to reliably fabricate 2D nanomaterial devices, such as 2D back-gated transistors and Q-HBTs, using standard fabrication processes. This can serve as a platform for future nanodevice developments as it paves the way towards the production of future advanced nano-scale devices.
In the proceeding section, the fabrication processes for 2D materials-based devices namely, the Q-HBT and 2D back-gated transistor are discussed in detail. Electron beam patterning combined with material location determination and metal electrode definition comprises the protocol since they are required in both mentioned processes. Part 1 discusses the step-by-step fabrication process of Q-HBTs20; and part 2 demonstrates a universal approach to obtain chemical vapor deposition (CVD) molybdenum disulfide (MoS2) back-gated transistors from transfer to lift-off21, which has been completely shown in the article. The detailed process flow is illustrated in (Figure 1).

<table border="0" cellpadding="0" cellspacing="0" style="width:973px;" width="973">
	<tbody>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">E-gun Evaporator</td>
			<td style="width:175px;">AST</td>
			<td style="width:255px;">PEVA 600I</td>
			<td style="width:296px;"></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Au slug, 99.99%</td>
			<td>Well-Being Enterprise Co</td>
			<td>&#160;N/A</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Ti slug, 99.99%</td>
			<td>Well-Being Enterprise Co</td>
			<td>&#160;N/A</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">E-beam Lithography System</td>
			<td style="width:175px;">Elionix</td>
			<td style="width:255px;">ELS7500-EX</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Cold Wall CVD System</td>
			<td style="width:175px;">Sulfur Science</td>
			<td style="width:255px;">SCW600S</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">C-plane Sapphire substrate</td>
			<td style="width:175px;">Summit-Tech</td>
			<td style="width:255px;">X171999</td>
			<td>(0001) &#177; 0.2 &#176; one side polished</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">100 nm SiO2/Si</td>
			<td style="width:175px;"></td>
			<td style="width:255px;"></td>
			<td>Fabricated in NDL</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Ammonia Solution</td>
			<td style="width:175px;">BASF</td>
			<td style="width:255px;">Ammonia Solution 28% Selectipur</td>
			<td style="width:296px;"></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Molybdenum (Mo), 99.95%</td>
			<td style="width:175px;">Summit-Tech&#160;</td>
			<td style="width:255px;">N/A</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Tungsten (W), 99.95%</td>
			<td style="width:175px;">Summit-Tech&#160;</td>
			<td style="width:255px;">N/A</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Sulfur (S), 99.5%</td>
			<td style="width:175px;">Sigma-Aldrich&#160;</td>
			<td style="width:255px;">13803</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Polymethyl Methacrylate (PMMA)</td>
			<td style="width:175px;">Microchem&#160;</td>
			<td style="width:255px;">8110788</td>
			<td>Use for transfer process</td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Spin Coater</td>
			<td>Laurell&#160;</td>
			<td>WS 400B 6NPP LITE</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Acetone</td>
			<td style="width:175px;">BASF</td>
			<td style="width:255px;">Acetone EL Selectipur</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Isopropanol (IPA)</td>
			<td style="width:175px;">BASF</td>
			<td style="width:255px;">2-Propanol UPS</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Photo Resist for EBL</td>
			<td style="width:175px;">TOK</td>
			<td style="width:255px;">TDUR-P-015</td>
			<td></td>
		</tr>
		<tr height="21">
			<td height="21" style="height:21px;width:248px;">Plasma Cleaner</td>
			<td style="width:175px;">Harrick Plasma</td>
			<td style="width:255px;">PDC-32G</td>
			<td>Oxygen plasma</td>
		</tr>
	</tbody>
</table>

a standard and reliable method to fabricate two-dimensional nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The device fabrication processes have been applied to several of the corresponding author&#39;s researches involving the development of 2D material devices. In this part, the results of some of these researches are presented to demonstrate the effectivity of the protocol discussed above. A monolayer of lateral WSe2-MoS2 Q-HBT20 is selected as the first example. Using the standard device fabrication processes detailed in the protocol, the monol...

Watch this Scientific Journal Video about A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics at JoVE.com

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

This method can help answer key questions in the field of 2D material device fabrication, related to techniques to precisely locate 2D material samples in the preparation for later fabrication steps. The main advantage of this technique is that this is tailored to the development of small-scale devices, for which finding the location of materials is more challenging. Demonstrating the procedure will be Po-Chun Chen and Kristan, research assistants and graduate students from my laboratory.The fabrication process requires two prepared substrates. The first is back-gated silicon dioxide on silicon with titanium and gold metal pad arrays. The second substrate is sapphire with a deposited layer of molybdenum disulfide.Take the sapphire substrate with the molybdenum disulfide to a spin coater. Spin coat PMMA to cover the top of the molybdenum disulfide at 3, 500 rpm for 30 seconds. Then, move the sample to a hot plate and bake it at 120 degrees Celsius for three minutes to strengthen the PMMA coating.Next, prepare 50 milliliters of ammonia solution. Immerse the sample to separate the molybdenum disulfide from the substrate. Once the film has separated, remove it from the ammonia solution.Transfer the molybdenum disulfide film to the silicon dioxide on the silicon substrate. To enhance adhesion, bake the sample at 120 degrees Celsius for at least 30 minutes. Recover the sample and place it in 30 milliliters of acetone.After about 30 minutes, the PMMA will be removed as indicated by a change in color. Before proceeding, rinse the sample in isopropyl alcohol and use nitrogen to blow it dry. Now, prepare to perform electron-beam lithography.Use an optical microscope to measure the displacement between the target locations and the alignment marks on the sample. Based on these measurements, design the metal electrode pattern layout using software. Spin coat Photo Resist on top of the sample and ensure it covers the entire sample.Move on to soft-bake the sample at 100 degrees Celsius for 90 seconds to enhance the adhesion. At the electron-beam lithography machine, upload the design and position the sample. The alignment marks in the silicon-silicon dioxide substrate should match the corresponding marks in the design.Expose the sample to the electron beam. When done, take the sample to a hot plate. Heat the sample to 120 degrees Celsius for 90 seconds in a post-exposure bake.Next, have a container of TMAH ready as a developer and immerse the sample for 80 seconds. Then, wash the sample in 200 milliliters of deionized water for 10 seconds. Examine the sample with an optical microscope to determine if the pattern is well developed.If it is well developed, hard-bake the sample at 110 degrees Celsius for 90 seconds. The next step is to use an electron gun evaporator to deposit 100 nanometers of gold on the sample. After deposition, work to remove the Photo Resist.To dissolve the Photo Resist, prepare 100 milliliters of acetone. Immerse the sample in the acetone to perform lift-off. Monitor the process with an optical microscope and stop when only metal lines and pads remain.During characterization, choose a source and a drain electrode from those in the device, then use an anatomic force microscope to apply a load to the sample. Here Xs indicate where loads have been applied. The atomic force microscope loads results in a compressive strain on the device.Here are the current voltage characteristics of the molybdenum disulfide device at different applied forces producing compressive strain. At a given voltage, the device's current decreases with an increase in applied force and vice versa, indicating a change in the resistance of the device, a behavior that is expected for a piezo sensor. These data are for the current response of the molybdenum disulfide device for repeated compressive strains at a fixed-bias voltage of one volt.The output current barely changes with the repeated application of 10 nanonewtons of applied force, suggesting that the sensor is stable. Once mastered and performed properly, this technique can be done in 20 straight hours, including the fabrication of all transistors. After its development, this technique can serve as the platform for future nanodevice developments as it paves the way towards the production of future advanced nanoscale devices.After watching this video, you should have a good understanding of how to reliably fabricate 2D back-gated transistors using standard fabrication processes, including electron beam lithography and metal electrodeposition. Though this method caters to the development of 2D nanomaterial devices, it can also be applied to 1D materials. Don't forget that working with TMAH, ammonia solution, PMMA, and other photo resistors can be extremely dangerous and personal protection equipment should always be worn while performing this procedure.

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