Name: fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology
Uploaded: 2015-12-07T13:00:00.000+00:00
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Description: Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

注意：使用する前に、関連するすべての物質安全データシート（MSDS）を参照してください。この製造工程で使用される化学物質のいくつかは、急性毒性と発癌性です。ナノ材料は、そのバルク対応物に比べて付加的な危険性を有していてもよいです。工学的制御（ヒュームフード）と個人用保護具（安全眼鏡、手袋、クリーンルーム服）の使用を含む、機器、化学物質やナノ材料を扱うときに、すべての適切な安全対策を使用してください。 リソグラフィ1.アライメントマーカ定義<ol><li>いずれかのnまたはp型ドーピング片面研磨工業用グレードのSi（100）ウエハーから開始します。 </li><li>コー​​トポジ型フォトレジストの1.4ミクロンを有するウェーハ。コー​​ルドプレート、適切な速度（3,500 rpm）でスピンコーティングし、90秒間ソフトベークAのウエハを冷却し、フォトレジストの接着を促進するために130℃で90秒間のヘキサメチルジシラザン（HMDS）処理を行いますトン95℃。 </li><li>フォトリソグラフィマスクを用いて露光ツールは、アライメントマーカを露光、露光量120ミリジュール/ cm 2です。 </li><li>シングルパドル現像プロセスを実行します。抵抗硬化させるために、100℃で、開発者と90秒のハードベークを用いて60秒の開発に続いて90秒115℃の露光後ベークを実行します。 </li><li>レジスト中の開口部が正しい寸法である場合に検査するために顕微鏡を使用してください。 </li><li>塩素プラズマエッチングを使用して120nmでのSiをエッチングします。この厚さは、この作品で使用される露光ツールの自動アライメントシステムのための良好なコントラストを提供します。 20/40 SCCM O 2 / CF 4、5 40分の80 SCCMのCl 2 / HBrの続くエッチングトル、500分の60 Wプラテン/ ICP RFパワー、10秒の酸化画期的な、たとえば誘導結合プラズマ（ICP）を使用して、 、60ミリトール、500分の20 Wプラテン/ ICP RFパワーは、35秒Siをエッチングします。 </li><li> endpoで1キロワット、400 SCCMのO 2（フォトレジストを除去するために酸素プラズマストリッパーを使用してくださいint型の検出と2分のオーバーエッチング）。フォトレジストは、アセトンのような通常の溶媒、プラズマによって硬化されるように使用することができません。 </li><li>ウエハを清掃してください。まず、水の抵抗率は5MΩ（有機クリーン）であるまでDI水ですすぎ、続いて99％HNO 3に 10分のためにそれらを置きます。水の抵抗率は5MΩ（清浄な金属）であるまで、110℃で65％HNO 3で10分間ウエハーこのクリーン後、DI水でリンスしました。ウェーハを乾燥させるためにリンサ乾燥機を使用してください。 </li></ol> 2.底部金属と層間絶縁膜の堆積<ol><li>経由テストの底部金属層を堆積させるために、マグネトロンスパッタ法を使用してください。 Tiを500 nmで、TiNの50nmであり、100nmのチタンを：3つの金属層のスタックを堆積する必要があります。最初のTi層は、スタックの抵抗を低減することで、TiNがCNTの成長のための実際の支持層であり、SiO 2層12をエッチングする際に上部Tiはプラズマダメージに対してのTiNを保護することです</suP&gt;。 Tiを350℃の基板温度でアルゴンプラズマと純Tiターゲットを用いたスパッタリング行います。 TiNの反応性スパッタリングを再度350℃の基板温度で、ArとN 2の組み合わせを使用します。 </li><li>プラズマ強化化学蒸着（PECVD）を用いて、SiO 2からなる厚さ1μmの層を堆積させます。ここにテトラエチルオルトシリケート（TEOS）は、350℃のプラテン温度で前駆体として使用されます。 <ol><li>適切なツールを使用してSiO 2層の厚さは、例えば、反射率計やエリプソメータを確認してください。 </li></ol></li><li>コー​​トコールドプレート、適切な速度（3,500 rpm）でスピンコーティング、およびソフト90秒でウエハの冷却に続いて130℃、90秒のHMDS処理を開始するポジ型フォトレジストの1.4ミクロン、ウエハ95℃で焼きます。 </li><li>フォトリソグラフィマスクおよび露光ツールを使用して、後にSiO 2トンにエッチングされる開口部の所望のパターンを露光Oアライメントマーカに整列ビアを形成し、露光量140ミリジュール/ cm 2です。 </li><li>開発者および100℃でハードベーク90秒を使用して、60秒の開発に続いて90秒間115℃の露光後ベーク、始まるシングルパドル現像プロセスを実行します。 </li><li>レジスト中の開口部が正しい寸法である場合とアライメントマーカにオーバーレイが正しいかどうかを検査するために顕微鏡を使用してください。 </li><li>プラズマは、SiO 2のコンタクト開口部をエッチングします。例えば、C 2 F 6とトライオードプラズマエッチャーを使用/ CHF 3 144分の36 SCCM 180ミリトール〜300 WのRF電力で。必要に応じて、時間の5％〜10％のオーバーエッチングを最小にするために、テストウェハ上にエッチング速度試験を行います。 注：Tiは、このフッ素化学の反応性エッチングに耐性があるが、プラズマへの長期暴露は、Ti層の物理的エッチングになります。 TiN層がプラズマにさらされている場合、これは負のinfluenを持っていますCNT 12の成長にCE。これが問題の部分4のトップメタライゼーションを作り、開口部のあ​​まり拡大につながるよう、ウェットエッチングを使用しないでください。 </li><li> 60秒間0.55％のHFでウェットエッチングにより犠牲Ti層を削除します。水の抵抗率までDI水でウェハをすすぐエッチングした後5MΩで、ウェーハを乾燥させるためにリンサ乾燥機を使用しています。 注：TiはメタリックグレイでありながらTi層をエッチングする場合には、確認することができる顕微鏡を使用して、TiN層は、金茶色を有することになります。 </li></ol> 3.触媒堆積とCNT成長<ol><li>電子ビーム蒸発器を用いてCoを5nmとを蒸発させます。少なくとも2×10 -6トールまでポンプダウンし、任意の水膜を除去するために堆積させる前に、真空下でランプを用いて60°Cにウエハを加熱します。フォトレジストのコンタクト開口部を定義するために使用さは、SiO 2のコンタクト開口に触媒の自己整合を提供するために、ウエハ上に維持されます。 </li><li>削除リフトオフによる接触開口部の外側のCo。 Coのためには、テトラヒドロフラン（THF）は、低温で最高のリフトオフの結果と成長を与えることが見出された。以前のFeを蒸発させた後、リフトオフのために使用したN -メチル-2-ピロリドン（NMP）は、損傷することが見出されました任意の配向CNTの成長を防止するために、共同あまりに程度。 35℃のTHFで超音波浴中で15分間ウェハを置きます。 5分間DI水ですすぎ、スピナー、窒素ガンを使用して乾燥させます。 </li><li>顕微鏡の下にウェハを検査し、レジスト残渣を確認してください。残留物が残っている場合、THF中の長い超音波処理を行い、必要に応じて手動で残基を払拭するために、リフトオフのために特別なソフト綿棒を使用しています。 </li><li>低圧化学蒸着（LPCVD）を用いて、CNTの成長を行います。 50 SCCMのC 2 H 2を追加することにより、CNTの成長に続いて80ミリバールで700 SCCMのH 2で350℃で8分間のプレアニーリング、次のレシピを使用してください。 350℃で、60成長の分はおよそ1ミクロンのCNTを与えます。必要に応じて調整するために、SiO 2層と同じ厚さであるべき高さを、テストの成長を行います。原子炉を冷却し、N 2を用いてパージします。 </li><li> 45°傾斜の下、または断面を調製することによって、開口部内部のCNTの高さを確認するために、走査型電子顕微鏡を使用してください。 </li><li> CNT 18の結晶化度を決定するために、ラマン分光法を用いてサンプルを検査します。 </li></ol> 4.トップサイドメタライゼーション<ol><li>上部金属を堆積させるために、マグネトロンスパッタリングを使用してください。 Tiは、CNT 19を接触させるための良い金属であるため、第1の真空を破ることなく、アル（1％のSi）の2ミクロン続いTiを100nmとし、スパッタ。 </li><li>より高い粘度のポジ型フォトレジストの3.1ミクロンでコートウェハを、コールドプレート、3000 rpmでスピンコートし、90秒間ソフトベークにウエハの冷却に続いて130℃、90秒のHMDS処理で始まります95°C。 </li><li>ミリジュール/ cm 2で、フォトリソグラフィマスクおよび露光ツールがアライメントマーカに合わせ上部金属パターンが露出-1フォーカス露光量420使っ。 </li><li>シングルパドル現像プロセスを実行します。これは、100℃で、開発者と90秒のハードベークを用いて60秒現像し、90秒間115℃の露光後ベークを開始します。 </li><li>レジスト中の行が正しい寸法である場合や、マーカーのオーバーレイが正しいかどうかを検査するために顕微鏡を使用してください。 </li><li>塩素プラズマエッチングを用いたTi / Alの積層体をエッチングします。 30/40 SCCMのCl 2 / HBrを、5ミリトール、終点検出および15/30 SCCMのCl 2 / HBrのを使用して、オーバーエッチ80％と500分の40 Wプラテン/ ICP RFパワー：誘導結合プラズマを用いて、例えば。 </li><li>フォトレジスト（1キロワット、終点検出、2分間のオーバーエッチングと400のSCCM O 2）を除去するために、酸素プラズマストリッパーを使用してください。金属被覆が完了していない場合（ すなわち、周りのピンホールが存在しますCNT）CNTに対するプラズマ損傷を防止するために、フォトレジストを除去するために、有機溶媒（ 例えば、NMP）を使用します。 </li><li>ウエハを清掃してください。水の抵抗率は5MΩ（有機クリーン）であるまでDI水ですすぎ、続いて99％HNO 3に 10分のためにそれらを置きます。ウェーハを乾燥させるためにリンサ乾燥機を使用してください。 </li></ol> 5.測定<ol><li>ウェハの上部メタライゼーションをチェックするために、製造業者の指示に従って、走査型電子顕微鏡を使用してください。 必要なウェーハを機械的に、図3に示すように、画像が得られ、90度のサンプルの傾きを使用してを介して完全なCNTをチェックするために切断することができる場合、サンプルは導電性であるように、追加の処理工程を使用する必要がなく、：注意サンプルは、直接SEMに装着することができます。一般的に、15または20キロボルトの高い加速電圧を使用することができるが、SiO 2層は、これは、Tを小さくすることができるあまりまで充電された場合5 kVのO。 </li><li> 図1及びVollebregt らに記載されるように、半導体パラメータアナライザと組み合わせてプローブステーションを用いて、4点探針IV測定を行う。16。 注意：相互接続の上に電位降下が理想的に小さいとして通常-0.5から0.5 Vの電圧掃引は、十分です。 4点プローブの設定を使用して、プローブ針とセットアップの配線抵抗の接触抵抗は省略しています。 </li></ol>

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M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Impact+of+the+atomic+layer+deposition+precursors+diffusion+on+solid-state+carbon+nanotube+based+supercapacitors+performances.">Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances.</a> Nanotechnology. 26 (6), 064002 (2015).</li></ol>

The authors have nothing to disclose.

図1は、本研究で作製した構造の概略図を表示し、これは、4点プローブ測定のために使用しました。電位は電流を運ぶないプローブにより測定されるように、中央のCNT束と金属との接点上に正確な電位降下（V H -V L）を測定することができます。より大きい直径のCNT束は、現在の強制プローブの全体の抵抗を低減し、中央のCNT束上に電位降下を最大にするために?...

銅とタングステンは、現在最先端の超大規模集積回路（VLSI）技術における相互接続のために使用される金属は、信頼性と電気伝導度1の面で彼らの物理的な限界に近づいています。ダウンスケーリングトランジスタは、一般的にそのパフォーマンスを改善するが、実際の抵抗及び配線の電流密度を増加させます。これは、遅延と電力消費2の観点の集積回路（IC）の性能を支配する相互接続をもたらしました。 CNTが簡単に縦3栽培されてできるようにカーボンナノチューブ（CNT）は、特に垂直相互接続（ビア）のために、CuとWメタライゼーションのための代替として提案されています。 CNTは、Cu 4よりも最大1,000倍高い電流密度を可能にする、優れた電気的信頼性を有することが示されています。また、CNTは、表面及び結晶粒界散乱を受けない、これは、rが増加していますナノメートルスケール5でのCuのesistivity。最後に、CNTは、VLSIチップの熱管理するのを助けることができる優れた熱伝導体6、であることが示されています。 VLSI技術におけるCNTの統合を成功のためには、CNTの成長プロセスは半導体製造と互換性がなされることが重要です。これは、材料及び大規模製造に適合し、かつスケーラブルであると考えられる装置を用いてCNT（&lt;400℃）での低温成長を必要とします。 CNT試験ビアの多くの例が文献7,8,9,10,11,12,13,14で実証されているが、これらのほとんどは、IC内の汚染物質15を製造すると考えられる触媒として鉄を使用します。また、これらの研究の多くで使用される成長温度は、400°Cの上限値よりもはるかに高いです。好ましくは、CNTはあっても、現代の低κ誘電体やフレキシブルとの統合を可能にするために、350℃以下で成長する必要があります基板。 ここでは、 触媒 16としてのCoを使用して350℃程度の低温でCNTを成長させるためのスケーラブルな方法を提示します。この方法は、相互接続と電極のスーパーキャパシタおよび電界放出素子までの集積回路に垂直配向CNTからなる別の電気構造を製造するために重要です。 TiNをしばしば使用するバリヤ材 7である間のCo触媒金属は、多くの場合、シリサイドの17の製造のためのIC製造で使用されます。また、私たちは、標準的な半導体製造の技術を使用しながら、CNT試験ビアを製造するためのプロセスを示します。これにより、CNT試験ビアは、製造される電子顕微鏡（SEM）及びラマン分光法を走査することによって検査され、電気的特徴。

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

この研究で使用した測定構造の設計は 、図1に見ることができる。プローブ、ワイヤ抵抗が回避されるように、CNT束の抵抗と金属CNTの接触抵抗の測定を正確に判定することができるような構造を採用することにより。束の抵抗は、CNT束の品質および濃度の尺度です。異なる長さの接触抵抗の束を決定するために測定すべきです。 45°の傾斜で金属...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

半導体技術との互換性低温カーボンナノチューブ垂直相互接続の作製

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Research

JoVE Journal

Engineering

7.6K ビュー.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

ビデオ: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

製造、ち密化、および3Dカーボンナノチューブの微細構造のレプリカ成形

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

工学

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

Nanoskivingによるナノギャップを作製

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

化学

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

カーボンナノチューブアレイの濡れ特性をチューニングするための処置をアニーリングドライ酸化と真空

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

任意の基板上の垂直配向小分子有機ナノワイヤーの超高密度アレイ

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

マイクロ流体浸透を通じて立体的微細構造ナノ複合材料の製造

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

シリコン直接ウェハー接合による均一ナノスケールキャビティの作製

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

高イオン強度ソリューションで感知するためのカーボンナノチューブ高周波ナノエレクトロニクスバイオセンサーの作製

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

生物工学

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

誘電泳動の流れ支援: 高性能低温硬化型ナノワイヤ デバイス作製のための低コストの方法

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

二次元ナノエレクトロニクスを作製する標準および信頼性の高いメソッド

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.

半導体技術との互換性低温カーボンナノチューブ垂直相互接続の作製

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製造、ち密化、および3Dカーボンナノチューブの微細構造のレプリカ成形

Nanoskivingによるナノギャップを作製

カーボンナノチューブアレイの濡れ特性をチューニングするための処置をアニーリングドライ酸化と真空

任意の基板上の垂直配向小分子有機ナノワイヤーの超高密度アレイ

マイクロ流体浸透を通じて立体的微細構造ナノ複合材料の製造

シリコン直接ウェハー接合による均一ナノスケールキャビティの作製

高イオン強度ソリューションで感知するためのカーボンナノチューブ高周波ナノエレクトロニクスバイオセンサーの作製

誘電泳動の流れ支援: 高性能低温硬化型ナノワイヤデバイス作製のための低コストの方法

二次元ナノエレクトロニクスを作製する標準および信頼性の高いメソッド

ハイスループット極低温電子顕微鏡のための厚さ制御されたマイクロパターンチップの作製

半導体技術との互換性低温カーボンナノチューブ垂直相互接続の作製

要約

さらに動画を探す

この動画の章

製造、ち密化、および3Dカーボンナノチューブの微細構造のレプリカ成形

Nanoskivingによるナノギャップを作製

カーボンナノチューブアレイの濡れ特性をチューニングするための処置をアニーリングドライ酸化と真空

任意の基板上の垂直配向小分子有機ナノワイヤーの超高密度アレイ

マイクロ流体浸透を通じて立体的微細構造ナノ複合材料の製造

シリコン直接ウェハー接合による均一ナノスケールキャビティの作製

高イオン強度ソリューションで感知するためのカーボンナノチューブ高周波ナノエレクトロニクスバイオセンサーの作製

誘電泳動の流れ支援: 高性能低温硬化型ナノワイヤ デバイス作製のための低コストの方法

二次元ナノエレクトロニクスを作製する標準および信頼性の高いメソッド

ハイスループット極低温電子顕微鏡のための厚さ制御されたマイクロパターンチップの作製

誘電泳動の流れ支援: 高性能低温硬化型ナノワイヤデバイス作製のための低コストの方法