Name: theoretical calculation and experimental verification for dislocation reduction in germanium epitaxial layers with semicylindrical voids on silicon
Uploaded: 2020-07-17T12:30:00
Description: Watch this Scientific Journal Video about Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon at JoVE.co

This work was financially supported by Japan Society for the Promotion of Science (JSPS) KAKENHI (17J10044) from the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. The fabrication processes were supported by &#34;Nanotechnology Platform&#34; (project No. 12024046), MEXT, Japan. The authors would like to thank Mr. K. Yamashita and Ms. S. Hirata, the University of Tokyo, for their help on TEM observations.

1. Theoretical calculation procedure
<ol>
	<li>Calculate trajectories of TDs. In the calculation, assume the SEG masks to be thin enough to ignore the ART effect on TDD reduction.
	<ol>
		<li>Determine growth surfaces and express them by equation(s). For instance, express the time evolution of a round-shaped cross-section of a SEG Ge layer with the time evolution parameter n = i, SEG Ge heights (hi) and SEG Ge radii (ri), as shown in the Supplemental Video 1a</st...

In the present work, TDD of 4 x 107/cm2 were experimentally shown. For further TDD reduction, there are mainly 2 critical steps within the protocol: SEG mask preparation and epitaxial Ge growth.
Our model shown in Figure 4 indicates that TDD can be reduced lower than 107/cm2 in coalesced Ge when APR, Wwindow/(Wwindow + Wmask), is as small as 0.1. Toward further TDD reduction, SEG masks wi...

Epitaxial Ge on Si has attracted substantial interests as an active photonic device platform since Ge can detect/emit light in the optical communication range (1.3-1.6 &#181;m) and is compatible with Si CMOS (complementary metal oxide semiconductor) processing techniques. However, since the lattice mismatch between Ge and Si is as large as 4.2%, threading dislocations (TDs) are formed in Ge epitaxial layers on Si at a density of ~109/cm2. The performances of Ge photonic devices are deteriorated by TDs because TDs works as carrier generation centers in Ge photodetectors (PDs) and modulators (MODs), and as carrier recombination centers in laser diodes (LDs). In turn, they would increase reverse leakage current (Jleak) in PDs and MODs1,2,3, and threshold current (Jth) in LDs4,5,6.
Various attempts have been reported to reduce TD density (TDD) in Ge on Si (Supplemental Figure 1). Thermal annealing stimulates movement of TDs leading to the reduction of TDD, typically to 2 x 107/cm2. The drawback is the possible intermixing of Si and Ge and out-diffusion of dopants in Ge such as phosphorus7,8,9 (Supplemental Figure 1a). The SiGe graded buffer layer10,11,12 increases the critical thicknesses and suppresses the generation of TDs leading to the reduction of TDD, typically to 2 x 106/cm2. The drawback here is that the thick buffer reduces light coupling efficiency between Ge devices and Si waveguides underneath (Supplemental Figure 1b). Aspect ratio trapping (ART)13,14,15 is a selective epitaxial growth (SEG) method and reduces TDs by trapping TDs at the sidewalls of thick SiO2 trenches, typically to &#60;1 x 106/cm2. The ART method uses a thick SiO2 mask to reduce TDD in Ge over the SiO2 masks, which locates far above Si and have the same drawback (Supplemental Figure 1b,1c). Ge growth on Si pillar seeds and annealing16,17,18 are similar to the ART method, enabling TD trapping by the high aspect ratio Ge growth, to &#60;1 x 105/cm2. However, high temperature annealing for Ge coalescence has the same drawbacks in Supplemental Figure 1a-c (Supplemental Figure 1d).
To achieve low-TDD Ge epitaxial growth on Si that is free from the drawbacks of the above-mentioned methods, we have proposed coalescence-induced TDD reduction19,20 based on the following two key observations reported so far in SEG Ge growth7,15,21,22,23: 1) TDs are bent to be normal to the growth surfaces (observed by the cross-sectional transmission electron microscope (TEM)), and 2) coalescence of SEG Ge layers results in the formation of semicylindrical voids over the SiO2 masks.
We have assumed that the TDs are bent owing to the image force from the growth surface. In the case of Ge on Si, the image force generates 1.38 GPa and 1.86 GPa shear stresses for screw dislocations and edge dislocations at distances 1 nm away from the free surfaces, respectively19. The calculated shear stresses are significantly larger than the Peierls stress of 0.5 GPa reported for 60&#176; dislocations in Ge24. The calculation predicts TDD reduction in Ge SEG layers on a quantitative basis and is in good agreement with the SEG Ge growth19. TEM observations of TDs are carried out to understand TD behaviors in the presented SEG Ge growth on Si20. The image-force-induced TDD reduction is free from any thermal annealing or thick buffer layers, and thus is more suitable for photonic device application.
In this article, we describe specific methods for the theoretical calculation and experimental verification employed in the proposing TDD reduction method.

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theoretical calculation and experimental verification for dislocation reduction in germanium epitaxial layers with semicylindrical voids on silicon

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the realization of monolithically integrated photonics circuits. The present paper describes methods of theoretical calculation and experimental verification of a novel model for the reduction of TDD. The method of theoretical calculation describes the bending of threading dislocations (TDs) based on the interaction of TDs and non-planar growth surfaces of selective epitaxial growth (SEG) in terms of dislocation image force. The calculation reveals that the presence of voids on SiO2 masks help to reduce TDD. Experimental verification is described by germanium (Ge) SEG, using an ultra-high vacuum chemical vapor deposition method and TD observations of the grown Ge via etching and cross-sectional transmission electron microscope (TEM). It is strongly suggested that the TDD reduction would be due to the presence of semicylindrical voids over the SiO2 SEG masks and growth temperature. For experimental verification, epitaxial Ge layers with semicylindrical voids are formed as the result of SEG of Ge layers and their coalescence. The experimentally obtained TDDs reproduce the calculated TDDs based on the theoretical model. Cross-sectional TEM observations reveal that both the termination and generation of TDs occur at semicylindrical voids. Plan-view TEM observations reveal a unique behavior of TDs in Ge with semicylindrical voids (i.e., TDs are bent to be parallel to the SEG masks and the Si substrate).

Theoretical Calculation
Figure 3&#160;shows&#160;calculated trajectories of TDs in 6 types of coalesced Ge layers: here, we define the aperture ratio (APR) to be Wwindow/(Wwindow + Wmask). Figure 3a shows a round-shaped SEG origin coalesced Ge of APR = 0.8. Here, 2/6 TDs are trapped. Figure 3b</stron...

Watch this Scientific Journal Video about Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon at JoVE.co

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Theoretical calculation and experimental verification are proposed for a reduction of threading dislocation (TD) density in germanium epitaxial layers with semicylindrical voids on silicon. Calculations based on the interaction of TDs and surface via image force, TD measurements, and transmission electron microscope observations of TDs are presented.

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the ...

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