Name: theoretical calculation and experimental verification for dislocation reduction in germanium epitaxial layers with semicylindrical voids on silicon
Uploaded: 2020-07-17T12:30:00.000+00:00
Duration: 6 min 57 s
Description: Watch this Scientific Journal Video about Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon at JoVE.co

This work was financially supported by Japan Society for the Promotion of Science (JSPS) KAKENHI (17J10044) from the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. The fabrication processes were supported by &#34;Nanotechnology Platform&#34; (project No. 12024046), MEXT, Japan. The authors would like to thank Mr. K. Yamashita and Ms. S. Hirata, the University of Tokyo, for their help on TEM observations.

1. Theoretical calculation procedure
<ol>
	<li>Calculate trajectories of TDs. In the calculation, assume the SEG masks to be thin enough to ignore the ART effect on TDD reduction.
	<ol>
		<li>Determine growth surfaces and express them by equation(s). For instance, express the time evolution of a round-shaped cross-section of a SEG Ge layer with the time evolution parameter n = i, SEG Ge heights (hi) and SEG Ge radii (ri), as shown in the Supplemental Video 1a and Eq. (1): 
		<img alt="Equation 4" src="/files/ftp_upload/58897/58897eq4.jpg" style="opacity: 0.9;" /></li>
		<li>Determine normal directions for an arbitrary location on the growth surfaces. For the round-shaped cross-section SEG Ge, describe the normal line at (xi&#160;,&#160;yi) as <img alt="Equation 7" src="/files/ftp_upload/58897/58897eq7v2.jpg" style="opacity: 0.9;" />, shown in Supplemental Video 1b as a red line. Then, obtain the edge of the TD (xi+1&#160;,&#160;yi+1) from the point (xi&#160;,&#160;yi) by solving the following simultaneous equations: 
		<img alt="Equation 10" src="/files/ftp_upload/58897/58897eq10.jpg" style="opacity: 0.9;" /></li>
		<li>Calculate a trajectory of one TD depending on the location of TD generation (x0, 0), as shown in Supplemental Video 1c. In other words, a trajectory for an arbitrary TD can be calculated by the method described above.</li>
		<li>Calculate TDD assuming that TDs penetrate to the bottom surface and contribute to the reduction of TDD (i.e., TDs below the point where SEG Ge layers coalesce are trapped by semicylindrical voids and never appear on the top surface).</li>
	</ol>
	</li>
</ol>
2. Experimental verification procedure
<ol>
	<li>SEG mask preparation
	<ol>
		<li>Prior to the fabrication of SEG masks, define Ge growth areas by preparing a design file. Inthe present work, prepare line-and-space patterns aligned to the [110] direction and square-shaped Si window areas of 4 mm in width using commercial software (e.g., AutoCAD).</li>
		<li>Determine the design of SEG masks(in particular Wwindow and Wmask)using the software.Wwindow is the window width (Si seed width) and Wmask is the SiO2 mask width, such that SEG Ge layers can coalesce with their adjacent ones. Determine Wwindow and Wmask by drawing rectangles by clicking open file &#8594; structure &#8594;&#160;rectangle or polyline. 
		NOTE: The width of the rectangles becomes Wwindow, and the interval of the rectangles becomes Wmask. In the present work, the minimum values of Wwindow and Wmask are 0.5 &#181;m and 0.3 &#181;m, respectively, which are restricted by the resolution in the employed EB lithography system.</li>
		<li>As references, draw square-shaped Si window areas of 4 mm in width D, regarded as the blanket areas. Click open file &#8594;&#160;structure &#8594;&#160;rectangle or polyline to draw the square-shaped Si window. Use the schematics shown in Figure 1 to prepare the line-and-space patterns and the 4 mm square blanket area.</li>
		<li>Prepare B-doped p-Si (001) substrates with the resistivity of 1-100 &#937;&#8729;cm. In the present work, use 4-inch Si substrates. Clean the substrate surfaces with Piranha solution (a mixture of 20 mL of 30% H2O2 and 80 mL of 96% H2SO4) as necessary.</li>
		<li>Open the lid on a tube furnace and load the Si substrates into the furnace using a glass rod. In the present work, oxidize 10 Si substrates at one time.</li>
		<li>Start to blow dry N2 gas into the furnace by opening the gas valve. Then, set the gas flow rate to 0.5 L/m by controlling the valve.</li>
		<li>Set the annealing temperature by changing the program. In the present work, use &#34;pattern step (mode 2)&#34; and set the process temperature to 900 &#176;C. Then, run the program by pushing function&#160;&#8594; run.</li>
		<li>As the temperature reaches 900 &#176;C, close the dry N2 valve, open the dry O2 valve (O2 flow = 1 L/m), and keep for 2 h. 
		NOTE: Perform steps 2.1.9-2.1.16 in a yellow room.</li>
		<li>Coat the oxidized Si substrates with a surfactant (OAP) using a spin coater and then bake at 110 &#176;C for 90 s on a hotplate.</li>
		<li>After the surfactant coating, coat the Si substrates with a photoresist (e.g., ZEP520A) using a spin coater and then bake at 180 &#176;C for 5 min on a hotplate.</li>
		<li>Load the Si substrates with the surfactant and photoresist into an electron beam (EB) writer.</li>
		<li>Read the design file (prepared in step 2.1.2) in the EB writer and make an operation file (WEC file). Set dose quantity as 120 &#181;C/cm2 in the WEC file. As the substrate loading finishes, perform EB exposure by clicking the single exposure button.</li>
		<li>Unload the substrate from the EB writer by clicking wafer carry &#8594;&#160;unload as the exposure finishes.</li>
		<li>Prepare a photoresist developer (ZED) and a rinse for the developer (ZMD) in a draft chamber. Dip the exposed Si substrates into the developer for 60 s at room temperature.</li>
		<li>Remove the Si substrates from the developer, and then dry the substrate with N2 gas.</li>
		<li>Put the developed Si substrates on a hotplate to bake at 110 &#176;C for 90 s.</li>
		<li>Dip the Si substrates into a buffered hydrofluoric acid (BHF-63SE) for 1 min in order to remove part of the SiO2 layers exposed to the air as the result of EB exposure and development.</li>
		<li>Remove the photoresist from the Si substrates by dipping into an organic photoresist remover (e.g., Hakuri-104) for 15 min.</li>
		<li>Dip the Si substrates into 0.5% diluted hydrofluoric acid for 4 min to remove the thin native oxide in the window regions but to retain the SiO2 masks. Then load onto an ultrahigh-vacuum chemical vapor deposition (UHV-CVD) chamber to grow Ge. Figure 2 shows the UHV-CVD system used in the present work.</li>
	</ol>
	</li>
	<li>Epitaxial Ge growth
	<ol>
		<li>Load the Si substrate with SEG masks (fabricated as in step 2.1) into a load lock chamber.</li>
		<li>Set the buffer/main growth temperature in the Recipe tab shown on the operation computer. Determine the durations for the main growth of Ge so that SEG Ge layers coalesce with adjacent ones. To decide the durations for the main growth, consider the growth rate of Ge on the {113} planes, which determines the growth in the in-plane/lateral direction26. In the present work, set the durations for the main growth as 270 min and 150 min for 650 &#176;C and 700 &#176;C, respectively.</li>
		<li>Click start in main window, and then the Si substrate is automatically transferred into the growth chamber. 
		NOTE: Protocol on epitaxial Ge growth (steps 2.2.4-2.2.7) is automatically processed.</li>
		<li>Grow Ge buffer on the loaded Si substrate at low-temperature (&#8776;380 &#176;C). Use GeH4 diluted at 9% in Ar as the source gas and keep the partial pressure of GeH4 for 0.5 Pa during the buffer growth.</li>
		<li>Grow Ge main layer at an elevated temperature. Keep the partial pressure of GeH4 for 0.8 Pa during the main growth. In the present work, use two different temperatures of 650 and 700 &#176;C for the main growth temperature in order to compare SEG Ge with a round-shaped cross-section and with a {113}-facetted cross-section25. 
		NOTE: The growth rate of Ge on the (001) plane was 11.7 nm/min independent of the temperature.</li>
		<li>In order to visualize the evolution of SEG Ge and their coalescence, perform Ge growth with periodic insertion of 10-nm-thick Si0.3Ge0.7 demarcation layers on another Si substrate. Si0.3Ge0.7 layers were formed using Si2H6 and GeH4 gases. During the Si0.3Ge0.7-layer growth, set the partial pressure of Si2H6 gas at 0.02 Pa and the partial pressure of GeH4 gas at 0.8 Pa.</li>
		<li>As the Si substrate is automatically transferred from the growth chamber to the load lock chamber, vent the load lock chamber and unload the Si substrate manually.</li>
	</ol>
	</li>
	<li>Etch pit density (EPD) measurements
	<ol>
		<li>Dissolve 32 mg of I2 in 67 mL of CH3COOH using an ultrasonic cleaning machine.</li>
		<li>Mix the I2-dissolved CH3COOH, 20 mL of HNO3, and 10 mL of HF.</li>
		<li>Dip the Ge-grown Si substrates into the CH3COOH/HNO3/HF/I2 solution for 5-7 s in order to form etched pits.</li>
		<li>Observe the etched Ge surfaces with an optical microscope (typically 100x) to ensure that etched pits are successfully formed.</li>
		<li>Employ an atomic force microscope (AFM) to count the etched pits. Put the etched Ge sample on an AFM stage, and then approach the probe by clicking auto approach.</li>
		<li>Decide the observation area using an optical microscope integrated with an AFM, and scan five different 10 &#181;m x 10 &#181;m areas. The amplitude damping factor is automatically determined.</li>
	</ol>
	</li>
	<li>TEM observations
	<ol>
		<li>Pick up TEM specimens from the coalesced/blanket Ge layers by using a focused Ge ion beam (FIB micro sampling method)27.</li>
		<li>Polish the TEM specimens in an ion milling system using Ar ions. In the present work, thin down TEM specimens for cross-sectional observations to be 150-500 nm in the [110] direction, and for plan-view observations to be 200 nm in the [001] direction.</li>
		<li>For plan-view TEM specimens, protect the top surfaces of the Ge layers with amorphous layers, and then thin down from the bottom (substrate) side of the Ge layers.</li>
		<li>Perform TEM observations under an acceleration voltage of 200 kV. Perform cross-sectional bright-field scanning TEM (STEM) observations in order to observe thick (500 nm) TEM specimens.</li>
		<li>For a coalesced Ge with Si0.3Ge0.7 demarcation layers, perform cross-sectional high-angle annular dark field (HAADF) STEM observations under an acceleration voltage of 200 kV.</li>
	</ol>
	</li>
</ol>

The authors have nothing to disclose.

In the present work, TDD of 4 x 107/cm2 were experimentally shown. For further TDD reduction, there are mainly 2 critical steps within the protocol: SEG mask preparation and epitaxial Ge growth.
Our model shown in Figure 4 indicates that TDD can be reduced lower than 107/cm2 in coalesced Ge when APR, Wwindow/(Wwindow + Wmask), is as small as 0.1. Toward further TDD reduction, SEG masks with smaller APR should be prepared. As mentioned in step 2.1.2, the minimum values of Wwindow and Wmask were 0.5 &#181;m and 0.3 &#181;m, respectively, limited by the resolution in the employed EB lithography system. One simple method to reduce APR is to modify lithography and etching processes (e.g., to use another photoresist, to use better lithography system, to use thinner SiO2 layers with shallower BHF etching, etc.). Mature lithography and etching process will enable SEG masks narrower than 100 nm. In the present work, coalesced Ge with a flat top surface were obtained when Wmask&#8804;1 &#181;m. Thus, Wwindow of 100 nm and Wmask of 900 nm (APR = 0.1) will give us coalesced Ge with flat top surface in the present growth conditions.
In addition to that, the modification of SEG mask preparation should bring less edge undulation of SEG masks, resulting in suppression of misorientation between Ge SEG layers. The TD generation when SEG Ge layers coalesce (Figure 11) will be suppressed as the result of the modification of SEG mask preparation.
As revealed by calculation results (Figure 3), suppression of Ge growth on SiO2 is required to reduce TDD. The suppression of Ge growth on SiO2 is brought by modification of Ge growth step (i.e., elevation of growth temperature, rotation of SEG mask, introduction of H2 gas, and reduction of the pressure of GeH4 gas44,45).
The TDD reduction method proposed/verified in the present work is superior to existing methods in terms of application for Ge photonic devices (i.e., TDD is reduced without any thermal annealing nor thick buffer layers). The maximum process temperature was 700 &#176;C, which is the growth temperature, and the height of the void was &#8776;150 nm. Compared with existing methods, the maximum temperature is lower than annealing temperature (typically 900 &#176;C)7, and height of the void is shallower than SiGe graded buffer layers (typically several &#181;m)10, SiO2 trenches for ART (typically 0.5-1 &#181;m)13, and buffer layer for Ge growth on Si pillars (typically &#8776;5 &#181;m)18. The comparison of conventional/presented methods are summarized in Table 1.
Considering the footprint of a typical Ge photonic device (&#8776;100 &#181;m2), TDD lower than 106/cm2, and a number of TD &#60; 1/device will be the final goal. Since the theoretical limit of TDD for this method is 0, TDD lower than 106/cm2 is potentially achievable. Toward the goal, more optimized lithography and etching will be investigated.

Epitaxial Ge on Si has attracted substantial interests as an active photonic device platform since Ge can detect/emit light in the optical communication range (1.3-1.6 &#181;m) and is compatible with Si CMOS (complementary metal oxide semiconductor) processing techniques. However, since the lattice mismatch between Ge and Si is as large as 4.2%, threading dislocations (TDs) are formed in Ge epitaxial layers on Si at a density of ~109/cm2. The performances of Ge photonic devices are deteriorated by TDs because TDs works as carrier generation centers in Ge photodetectors (PDs) and modulators (MODs), and as carrier recombination centers in laser diodes (LDs). In turn, they would increase reverse leakage current (Jleak) in PDs and MODs1,2,3, and threshold current (Jth) in LDs4,5,6.
Various attempts have been reported to reduce TD density (TDD) in Ge on Si (Supplemental Figure 1). Thermal annealing stimulates movement of TDs leading to the reduction of TDD, typically to 2 x 107/cm2. The drawback is the possible intermixing of Si and Ge and out-diffusion of dopants in Ge such as phosphorus7,8,9 (Supplemental Figure 1a). The SiGe graded buffer layer10,11,12 increases the critical thicknesses and suppresses the generation of TDs leading to the reduction of TDD, typically to 2 x 106/cm2. The drawback here is that the thick buffer reduces light coupling efficiency between Ge devices and Si waveguides underneath (Supplemental Figure 1b). Aspect ratio trapping (ART)13,14,15 is a selective epitaxial growth (SEG) method and reduces TDs by trapping TDs at the sidewalls of thick SiO2 trenches, typically to &#60;1 x 106/cm2. The ART method uses a thick SiO2 mask to reduce TDD in Ge over the SiO2 masks, which locates far above Si and have the same drawback (Supplemental Figure 1b,1c). Ge growth on Si pillar seeds and annealing16,17,18 are similar to the ART method, enabling TD trapping by the high aspect ratio Ge growth, to &#60;1 x 105/cm2. However, high temperature annealing for Ge coalescence has the same drawbacks in Supplemental Figure 1a-c (Supplemental Figure 1d).
To achieve low-TDD Ge epitaxial growth on Si that is free from the drawbacks of the above-mentioned methods, we have proposed coalescence-induced TDD reduction19,20 based on the following two key observations reported so far in SEG Ge growth7,15,21,22,23: 1) TDs are bent to be normal to the growth surfaces (observed by the cross-sectional transmission electron microscope (TEM)), and 2) coalescence of SEG Ge layers results in the formation of semicylindrical voids over the SiO2 masks.
We have assumed that the TDs are bent owing to the image force from the growth surface. In the case of Ge on Si, the image force generates 1.38 GPa and 1.86 GPa shear stresses for screw dislocations and edge dislocations at distances 1 nm away from the free surfaces, respectively19. The calculated shear stresses are significantly larger than the Peierls stress of 0.5 GPa reported for 60&#176; dislocations in Ge24. The calculation predicts TDD reduction in Ge SEG layers on a quantitative basis and is in good agreement with the SEG Ge growth19. TEM observations of TDs are carried out to understand TD behaviors in the presented SEG Ge growth on Si20. The image-force-induced TDD reduction is free from any thermal annealing or thick buffer layers, and thus is more suitable for photonic device application.
In this article, we describe specific methods for the theoretical calculation and experimental verification employed in the proposing TDD reduction method.

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theoretical calculation and experimental verification for dislocation reduction in germanium epitaxial layers with semicylindrical voids on silicon

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the realization of monolithically integrated photonics circuits. The present paper describes methods of theoretical calculation and experimental verification of a novel model for the reduction of TDD. The method of theoretical calculation describes the bending of threading dislocations (TDs) based on the interaction of TDs and non-planar growth surfaces of selective epitaxial growth (SEG) in terms of dislocation image force. The calculation reveals that the presence of voids on SiO2 masks help to reduce TDD. Experimental verification is described by germanium (Ge) SEG, using an ultra-high vacuum chemical vapor deposition method and TD observations of the grown Ge via etching and cross-sectional transmission electron microscope (TEM). It is strongly suggested that the TDD reduction would be due to the presence of semicylindrical voids over the SiO2 SEG masks and growth temperature. For experimental verification, epitaxial Ge layers with semicylindrical voids are formed as the result of SEG of Ge layers and their coalescence. The experimentally obtained TDDs reproduce the calculated TDDs based on the theoretical model. Cross-sectional TEM observations reveal that both the termination and generation of TDs occur at semicylindrical voids. Plan-view TEM observations reveal a unique behavior of TDs in Ge with semicylindrical voids (i.e., TDs are bent to be parallel to the SEG masks and the Si substrate).

Watch this Scientific Journal Video about Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon at JoVE.co

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Theoretical calculation and experimental verification are proposed for a reduction of threading dislocation (TD) density in germanium epitaxial layers with semicylindrical voids on silicon. Calculations based on the interaction of TDs and surface via image force, TD measurements, and transmission electron microscope observations of TDs are presented.

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the ...

theoretical-calculation-experimental-verification-for-dislocation

Nanyang Technological University

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JoVE Journal

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2.1K Views.  The University of Tokyo. Theoretical calculation and experimental verification are proposed for a reduction of threading dislocation (TD) density in germanium epitaxial layers with semicylindrical voids on silicon. Calculations based on the interaction of TDs and surface via image force, TD measurements, and transmission electron microscope observations of TDs are presented. 

Video: Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

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Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

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The use of electron channeling contrast imaging in a scanning electron microscope to characterize defects in III-V/Si heteroexpitaxial thin films is described. This method yields similar results to plan-view transmission electron microscopy, but in significantly less time due to lack of required sample preparation.

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Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

A procedure to measure the bulk lifetime (&#62;100 &#181;sec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min&#160;using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (&#60;1012 cm-3).

A RT liquid surface passivation technique to investigate the recombination activity of bulk silicon defects is described. For the technique to be successful, three critical steps are required: (i) chemical cleaning and etching of silicon, (ii) immersion of silicon in 15% hydrofluoric acid and (iii) illumination for 1 min.

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Epitaxial Growth of Perovskite Strontium Titanate on Germanium via Atomic Layer Deposition

Atomic layer deposition (ALD) is a commercially utilized deposition method for electronic materials. ALD growth of thin films offers thickness control and conformality by taking advantage of self-limiting reactions between vapor-phase precursors and the growing film. Perovskite oxides present potential for next-generation electronic materials, but to-date have mostly been deposited by physical methods. This work outlines a method for depositing SrTiO3 (STO) on germanium using ALD. Germanium has higher carrier mobilities than silicon and therefore offers an alternative semiconductor material with faster device operation. This method takes advantage of the instability of germanium's native oxide by using thermal deoxidation to clean and reconstruct the Ge (001) surface to the 2&#215;1 structure. 2-nm thick, amorphous STO is then deposited by ALD. The STO film is annealed under ultra-high vacuum and crystallizes on the reconstructed Ge surface. Reflection high-energy electron diffraction (RHEED) is used during this annealing step to monitor the STO crystallization. The thin, crystalline layer of STO acts as a template for subsequent growth of STO that is crystalline as-grown, as confirmed by RHEED. In situ X-ray photoelectron spectroscopy is used to verify film stoichiometry before and after the annealing step, as well as after subsequent STO growth. This procedure provides framework for additional perovskite oxides to be deposited on semiconductors via chemical methods in addition to the integration of more sophisticated heterostructures already achievable by physical methods.

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Chemistry

Comprehensive Characterization of Extended Defects in Semiconductor Materials by a Scanning Electron Microscope

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The optical, electrical, and structural properties of dislocations and of grain boundaries in semiconductor materials can be determined by experiments performed in a scanning electron microscope. Electron microscopy has been used to investigate cathodoluminescence, electron beam induced current, and diffraction of backscattered electrons.

Extended defects such as dislocations and grain boundaries have a strong influence on the performance of microelectronic devices and on other applications ...

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

This paper reports an array-designed C84-embedded Si substrate fabricated using a controlled self-assembly method in an ultra-high vacuum chamber. The characteristics of the C84-embedded Si surface, such as atomic resolution topography, local electronic density of states, band gap energy, field emission properties, nanomechanical stiffness, and surface magnetism, were examined using a variety of surface analysis techniques under ultra, high vacuum (UHV) conditions as well as in an atmospheric system. Experimental results demonstrate the high uniformity of the C84-embedded Si surface fabricated using a controlled self-assembly nanotechnology mechanism, represents an important development in the application of field emission display (FED), optoelectronic device fabrication, MEMS cutting tools, and in efforts to find a suitable replacement for carbide semiconductors. Molecular dynamics (MD) method with semi-empirical potential can be used to study the nanoindentation of C84-embedded Si substrate. A detailed description for performing MD simulation is presented here. Details for a comprehensive study on mechanical analysis of MD simulation such as indentation force, Young&#39;s modulus, surface stiffness, atomic stress, and atomic strain are included. The atomic stress and von-Mises strain distributions of the indentation model can be calculated to monitor deformation mechanism with time evaluation in atomistic level.

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

This paper reports the nanomaterial fabrication of a fullerene Si substrate inspected and verified by nanomeasurements and molecular dynamic simulation.

This paper reports an array-designed C84-embedded Si substrate fabricated using a controlled self-assembly method in an ultra-high vacuum chamber. The ...

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and forging. Adoption of this technique is proceeding despite disagreement concerning the underlying mechanism responsible for EAD. The experimental procedure described herein enables a more explicit study compared to previous EAD research by removing thermal effects, which are responsible for disagreement in interpreting previous EAD results. Furthermore, as the procedure described here enables EAD observation in situ and in real time in a transmission electron microscope (TEM), it is superior to existing post-mortem methods that observe EAD effects post-test. Test samples consist of a single crystal copper (SCC) foil having a free-standing tensile test section of nanoscale thickness, fabricated using a combination of laser and ion beam milling. The SCC is mounted to an etched silicon base that provides mechanical support and electrical isolation while serving as a heat sink. Using this geometry, even at high current density (~3,500 A/mm2), the test section experiences a negligible temperature increase (&#60;0.02 &#176;C), thus eliminating Joule heating effects. Monitoring material deformation and identifying the corresponding changes to microstructures, e.g. dislocations, are accomplished by acquiring and analyzing a series of TEM images. Our sample preparation and in situ experiment procedures are robust and versatile as they can be readily utilized to test materials with different microstructures, e.g., single and polycrystalline copper.

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Isolating electrical and thermal effects on electrically assisted deformation (EAD) is very difficult using macroscopic samples. Metallic sample micro- and nanostructures together with a custom test procedure have been developed to evaluate the impact of applied current on the formation without joule heating and evolution of dislocations on these samples.

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and ...

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface between two different materials is necessary. The S-Sm junction with high interface transparency will then facilitate the observation of the induced hard superconducting gap, which is the key requirement to access the topological phases (TPs) and observation of exotic quasiparticles such as Majorana zero modes (MZM) in hybrid systems. A material platform that can support observation of TPs and allows the realization of complex and branched geometries is therefore highly demanding in quantum processing and computing science and technology. Here, we introduce a two-dimensional material system and study the proximity induced superconductivity in semiconducting two-dimensional electron gas (2DEG) that is the basis of a hybrid quantum integrated circuit (QIC). The 2DEG is a 30 nm thick In0.75Ga0.25As quantum well that is buried between two In0.75Al0.25As barriers in a heterostructure. Niobium (Nb) films are used as the superconducting electrodes to form Nb- In0.75Ga0.25As -Nb Josephson junctions (JJs) that are symmetric, planar and ballistic. Two different approaches were used to form the JJs and QICs. The long junctions were fabricated photolithographically, but e-beam lithography was used for short junctions&#8217; fabrication. The coherent quantum transport measurements as a function of temperature in the presence/absence of magnetic field B are discussed. In both device fabrication approaches, the proximity induced superconducting properties were observed in the In0.75Ga0.25As 2DEG. It was found that e-beam lithographically patterned JJs of shorter lengths result in observation of induced superconducting gap at much higher temperature ranges. The results that are reproducible and clean suggesting that the hybrid 2D JJs and QICs based on In0.75Ga0.25As quantum wells could be a promising material platform to realize the real complex and scalable electronic and photonic quantum circuitry and devices.

Quantum integrated circuits (QICs) consisting of array of planar and ballistic Josephson junctions (JJs) based on In0.75Ga0.25As two-dimensional electron gas (2DEG) is demonstrated. Two different methods for fabrication of the two-dimensional (2D) JJs and QICs are discussed followed by the demonstration of quantum transport measurements in sub-Kelvin temperatures.

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface ...

Developing High Performance GaP/Si Heterojunction Solar Cells

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar cells. In this work, we present high performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime and high crystal quality of epitaxial GaP layers. It is shown that by applying phosphorus (P)-diffusion layers into the Si substrate and a SiNx layer, the Si minority-carrier lifetime can be well-maintained during the GaP growth in the molecular beam epitaxy (MBE). By controlling the growth conditions, the high crystal quality of GaP was grown on the P-rich Si surface. The film quality is characterized by atomic force microscopy and high-resolution x-ray diffraction. In addition, MoOx was implemented as a hole-selective contact that led to a significant increase in the short-circuit current density. The achieved high device performance of the GaP/Si heterojunction solar cells establishes a path for further enhancement of the performance of Si-based photovoltaic devices.

Here, we present a protocol to develop high-performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime.

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar ...

3D Depth Profile Reconstruction of Segregated Impurities Using Secondary Ion Mass Spectrometry

The presented protocol combines excellent detection limits (1 ppm to 1 ppb) using secondary ion mass spectrometry (SIMS) with reasonable spatial resolution (~1 &#181;m). Furthermore, it describes how to obtain realistic three-dimensional (3D) distributions of segregated impurities/dopants in solid state materials. Direct 3D depth profile reconstruction is often difficult to achieve due to SIMS-related measurement artifacts. Presented here is a method to identify and solve this challenge. Three major issues are discussed, including the i) nonuniformity of the detector being compensated by flat-field correction; ii) vacuum background contribution (parasitic oxygen counts from residual gases present in the analysis chamber) being estimated and subtracted; and iii)&#160;performance of all steps within a stable timespan of the primary ion source. Wet chemical etching is used to reveal the position and types of dislocation in a material, then the SIMS result is superimposed on images obtained via scanning electron microscopy (SEM). Thus, the position of agglomerated impurities can be related to the position of certain defects. The method is fast and does not require sophisticated sample preparation stage; however, it requires a high-quality, stable ion source, and the entire measurement must be performed quickly to avoid deterioration of the primary beam parameters.

The presented method describes how to identify and solve measurement artifacts related to secondary ion mass spectrometry as well as obtain realistic 3D distributions of impurities/dopants in solid state materials.

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Summary

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Chapters in this video

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Electron Channeling Contrast Imaging for Rapid III-V Heteroepitaxial Characterization

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

Epitaxial Growth of Perovskite Strontium Titanate on Germanium via Atomic Layer Deposition

Comprehensive Characterization of Extended Defects in Semiconductor Materials by a Scanning Electron Microscope

Probing C₈₄-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Developing High Performance GaP/Si Heterojunction Solar Cells

3D Depth Profile Reconstruction of Segregated Impurities Using Secondary Ion Mass Spectrometry